Abstract: Described is a transducer head assembly for magnetic disk files, the assembly using the informational data itself recorded on the disk in the form of a plurality of annular tracks for precisely positioning the head assembly with respect to the individual tracks. For this purpose, the assembly includes an upper head cooperable with the upper face of the record disk and a lower head cooperable with the lower face of the record disk, the lower head being spaced from the upper head one-half the distance between a pair of adjacent tracks such that one head may be used for positioning purposes by centering same between two adjacent tracks on the respective face of the disk, while the other head being thereby centered with a track on its respective face of the disk, may be used for recording, reproducing or erasing data with respect to the later track.

Abstract: A drive system for a plurality of inductive loads comprises a load energizing circuit for each inductive load, means connecting a DC voltage across all the circuits in parallel, and a switching device in each circuit selectively actuatable to energize the loads according to a predetermined sequence. The system also includes an energy storage circuit for each load energizing circuit having a capacitor charged by the collapse of the magnetic field in its respective inductive load when the latter's switching device is switched-off. Further included is an energy transfer circuit for each load energizing circuit to transfer the energy stored in the capacitor of one inductive load by the collapse of the magnetic field therein, when its switching device is switched-on, to the load energizing circuit of the inductive load next switched-on by its switching device.

Abstract: A flip-flop controlled clock gating system comprises a single-shot clock circuit including triggerable means effective to allow the passage of only one clock pulse from the clock input terminal to the output terminal; a clock inhibit circuit including a flip-flop network settable in a first condition enabling the passage of clock pulses from the input to the output terminal and STOP actuator means effective to actuate the flip-flop network to a second condition inhibiting the passage of such clock pulses; and a clock enable circuit including RUN actuator means effective when actuated to trigger the single-shot clock circuit to restore the flip-flop network to its first condition enabling the passage of clock pulses from the input terminal to its output terminal.

Abstract: A vandal-resistant gate which is constructed in such a manner that it only opens wide enough to accommodate a credit card but not coins or other foreign objects. In this manner the gate allows the entry of a credit card but resists the insertion of coins or other objects which would immobilize the machine.

Abstract: A controller implemented on a single LSI MOS chip is described for linking a typewriter console to a processor unit. The controller comprises a FIFO (First-In-First-Out) buffer for storing the keyboard data characters read-out from the console. The buffer includes a flag for each stage, each flag being controlled to assume a first condition when its respective stage is occupied by a character, and a second condition when it is vacant of a character. The keyboard data characters are inputted into the first stage by strobe pulses, and are continuously shifted by high-speed clock pulses to the highest stage of the buffer whose flag is in the stage-vacant condition, the characters being read-out from the last stage. The buffer includes means for preventing the entry of a new character, and also for providing an indication of an "Overflow" condition, whenever a strobe pulse is received by the buffer while the first-stage flag of the buffer is in the stage-occupied condition.

Abstract: Method and apparatus are described for storing and retrieving data in the form of double-frequency coherent-phase signals having a plurality of "n" data bits, and particularly for making a parity check of such data. To make the parity check, the level of the signal is sampled at a first point between the beginning and middle of the first data bit, and at a second point between the middle and the end of the "n"th data bit. The levels of the two samples are compared, and a parity bit is generated of a level determined by whether "n" is an odd or even number, and whether there is to be odd or even parity. Described is a parity generating means in the form of an EXCLUSIVE-OR logical network to provide odd parity when "n" is an even number, or to provide even parity when "n" is an odd number. Also described is an equivalent logical network which can be used for effecting an even parity check when "n" is an even number, or an odd parity check when "n" is an odd number.