Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a liquid on a region of a die, and then forming an identification mark through the liquid on the die.

Abstract: Methods and associated structures of forming an indium containing solder material directly on an active region of a copper IHS is enabled. A copper indium containing solder intermetallic is formed on the active region of the IHS. The solder intermetallic improves the solder-TIM integration process for microelectronic packaging applications.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of functionalized nanaparticles on a substrate by immersing the substrate in at least one of a solvent and a polymer matrix, wherein at least one of the solvent and the polymer matrix comprises a plurality of functionalized nanoparticles; and forming a second layer of functionalized nanoparticles on the first layer of functionalized particles, wherein there is a gradient in a property between the first layer and the second layer.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include method of forming a layered nanotube structure comprising a wetting layer disposed on a nanotube, a Shottky layer disposed on the wetting layer, a barrier layer disposed on the Shottky layer, and a matrix layer disposed on the barrier layer.

Abstract: Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.

Abstract: A microelectronic substrate, a method of forming the same, and a system including the same. The microelectronic substrate comprises: a conductive layer; a spacer layer disposed onto the conductive dielectric layer; a dielectric build-up layer disposed onto the spacer layer, the spacer layer being made of a material that has a lower shrinkage than a material of the embedding dielectric-build-up layer during curing, and a higher viscosity than a material of the embedding dielectric build-up layer in its pre-cure form and during curing; and active or passive microelectronic components embedded within the dielectric build-up layer.

Abstract: A printed circuit board includes a group of pads suitable to be soldered to a respective group of solder-balls of a device. Each pad of the group has a crack initiation point on its perimeter at a location where cracks in a solder-ball are anticipated to start after that solder-ball is soldered to that pad. For a pad of that group having a microvia located therein, a center of that microvia is located farther than a center of that pad from its crack initiation point. For a pad of that group having a trace merging along a portion of its perimeter, that portion does not include a vicinity of that crack initiation point.

Abstract: Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a conductive material in an interconnect opening within an interlayer dielectric material that is disposed on a substrate, forming a low density dielectric material on a surface of the dielectric layer and on a surface of the conductive material, and forming a high density dielectric barrier layer on the low density dielectric layer.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a magnetic material on a substrate, wherein the magnetic material comprises rhenium, cobalt, iron and phosphorus, and annealing the magnetic material at a temperature below about 330 degrees Celsius, wherein the coercivity of the annealed magnetic material is below about 1 Oersted.

Abstract: Embodiments of the invention provide a first component with a compliant interconnect bonded to a second component with a land pad by a metal to metal bond. In some embodiments, the first component may be a microprocessor die and the second component a package substrate.

Abstract: Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate layer on the gate dielectric layer, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air.

Abstract: Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.

Abstract: An embodiment of the present invention is a technique to construct a multi-die package. A stack of dice is formed from a base substrate in a package. The dice are positioned one on top of another and have copper plated segments for die interconnection. The dice are interconnected using copper plating to connect the copper plated segments.

Abstract: Devices and methods for their formation, including electronic devices containing capacitors, are described. In one embodiment, a device includes a substrate and a capacitor is formed on the substrate. The capacitor includes first and second electrodes and a capacitor dielectric between the first and second electrodes. At least one of the first and second electrodes includes a metal layer having carbon nanotubes coupled thereto. In one aspect of certain embodiments, the carbon nanotubes are at least partially coated with an electrically conductive material. In another aspect of certain embodiments, the substrate comprises an organic substrate and the capacitor dielectric comprises a polymer material. Other embodiments are described and claimed.

Abstract: Methods of forming microelectronic device structures are described. Those methods may include forming a passivation layer on a substrate, wherein the substrate comprises an array of conductive structures, forming a first via in the passivation layer, forming a second via in the passivation layer that exposes at least one of the conductive structures in the array, and wherein the second via is formed within the first via space to form a step via, and forming a conductive material in the step via, wherein a round dimple is formed in the conductive material.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those structures may comprise a transistor comprising a metal gate disposed on a gate dielectric that is disposed on a substrate, and a source/drain region disposed adjacent a channel region of the transistor. The source/drain region comprises a source/drain extension comprising a vertex point, wherein a top surface of the channel region is substantially planar with the vertex point.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a first plurality of openings through a first surface of a substrate, forming a p-type TFTEC material within the first plurality of openings, forming a second plurality of openings substantially adjacent to the first plurality of openings through the first surface of the substrate, and then forming an n-type TFTEC material within the second plurality of openings.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include amorphizing at least one contact area of a source/drain region of a transistor structure by implanting through at least one contact opening, forming a first layer of metal on the at least one contact area, forming a second layer of metal on the first layer of metal, selectively etching a portion of the second metal layer, annealing the at least one contact area to form at least one silicide, and removing the unreacted first metal layer and second metal layer from the transistor structure and forming a conductive material in the at least one contact opening.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a first plurality of openings through a first surface of a substrate, forming a p-type TFTEC material within the first plurality of openings, forming a second plurality of openings substantially adjacent to the first plurality of openings through the first surface of the substrate, and then forming an n-type TFTEC material within the second plurality of openings.