Patents Represented by Attorney Kathy Ortiz

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  • Microelectronic package having solder-filled through-vias
    Patent number: 7638867
    Abstract: An apparatus, a method, and a system associated with microelectronic packaging are disclosed herein. In various embodiments, a microelectronic package may include a die having one or more through-vias, each filled with a solder material; a substrate; and one or more solder bumps disposed between and electrically connecting the substrate and a backside of the die.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: December 29, 2009
    Assignee: Intel Corporation
    Inventors: Dingying Xu, Dale A. Hackitt
  • Sealing porous dielectric materials
    Patent number: 7560165
    Abstract: Method and structure for minimizing the downsides associated with microelectronic device processing adjacent porous dielectric materials are disclosed. In particular, chemical protocols are disclosed wherein porous dielectric materials may besealed by attaching coupling agents to the surfaces of pores. The coupling agents may form all or part of caps on reactive groups in the dielectric surface or may crosslink to seal pores in the dielectric.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: July 14, 2009
    Assignee: Intel Corporation
    Inventors: Grant Kloster, Robert P. Meagley, Michael D. Goodner, Kevin P. O'brien, Don Bruner
  • Localized microelectronic cooling
    Patent number: 7430870
    Abstract: An apparatus and associated method to provide localized cooling to a microelectronic device are generally described. In this regard, according to one example embodiment, a cooling system comprising one or more thermoelectric cooler(s) is thermally coupled to a heat spreader to provide cooling to one or more hot spot(s) of a microelectronic device.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: October 7, 2008
    Assignee: Intel Corporation
    Inventors: David S. Chau, Gregory M. Chrysler
  • Substrate conductive post formation
    Patent number: 7358116
    Abstract: A substrate with at least one conductive post formed prior to the formation of an inter-layer dielectric (ILD) coating on the substrate. The conductive post may be formed from a metal layer of the substrate. Additionally, the conductive post may be built up on the substrate.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: April 15, 2008
    Assignee: Intel Corporation
    Inventor: Boyd L. Coomer
  • Selective deposition to improve selectivity and structures formed thereby
    Patent number: 7358547
    Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: April 15, 2008
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Nayanee Gupta, Chris Auth, Glenn A. Glass
  • Tri-gate device with conformal PVD workfunction metal on its three-dimensional body and fabrication method thereof
    Patent number: 7354832
    Abstract: A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: April 8, 2008
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Brian S. Doyle, Jack T. Kavalieros, Uday Shah
  • Functionalization and separation of nanotubes and structures formed thereby
    Patent number: 7335258
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include attaching at least one functional group to a chondroitin sulfate molecule, and then attaching the at least one functional group to a carbon nanotube, wherein the carbon nanotube is made soluble in a solution.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: February 26, 2008
    Assignee: Intel Corporation
    Inventors: Yuegang Zhang, Robert J. Chen