Abstract: An engine which employs a cam follower mechanism to reduce wear and reduce the size of an assembled engine. The cam follower mechanism utilizes guide rails located to reduce side thrust on the valve stem. The engine employs a high speed quill shaft to synchronize independent cam shafts existing in each of a plurality of interconnected engines. The engine is assembled using a single size fastener to provide a uniform stress gradient within the engine. The engines are interconnected utilizing O-ring seals. The engine provides a piston crown utilizing a connecting rod directly connected to the bottom surface of the piston crown. The piston crown is stabilized along the longitudinal cylinder axis by a rail guide. Connecting rods are provided which require less than one hundred eighty degrees (180.degree.) circumference of a crankshaft pin for support so that a plurality of connecting rods can be associated with a single crankshaft pin.

Abstract: Via filling is enhanced by the techniques of 1) providing pillars immediately underneath semiconductor features, such as metal layer contacts (inter-connection points), and 2) polishing off excess via-filling material so that the via-filling plug is flush with the topmost insulating layer. The pillars are provided under every feature over which a via will be formed, so that an insulating layer surrounding the via will be thinner at the location of the feature. If necessary, polishing is continued to thin the insulating layer so that the plugs in initially selectively under-filled vias are made flush with the insulating layer. Method and apparatus are disclosed.

Abstract: A technique for integrated circuit floorplanning using irregularly shaped dies (e.g., triangular, elongated rectangular, parallelogram-shaped, etc.) is described whereby the layout of the integrated circuit die is accomplished by partitioning (slicing) the die into progressively smaller groups of more than two areas into which functions (active elements, or circuits) are assigned according to their area requirements. The die is iteratively sub-partitioned.

Abstract: The present invention provides a method for fabricating an integrated circuit package, as well the resulting integrated circuit package, which retains a heatsink in close communication with a mold cavity. This precludes any encapsulant from flowing between the heatsink and the inner surface of a mold cavity. As a consequence, the bottom of the heatsink is not encapsulated and is thus exposed. This is accomplished by including posts, attached to the leadframe assembly, which have the function of exerting a downward force on a leadframe assembly and, in turn, on the heatsink. Tie bars, which are non-functional parts of a leadframe assembly, can be utilized as posts by bending the posts into an upright position.

Abstract: A method and apparatus for testing semiconductor devices at device operating speed for both proper combinational and timing logic functions with a standard low speed logic tester. A high speed phase-lock-loop system clock of the semiconductor device is frequency and phase locked to the lower speed logic tester clock. Test data is shifted into the semiconductor device at the test clock speed. Two controlled system clock pulses are utilized to clock the test data into the semiconductor devices. The first of these two pulses starts the test and the second ends the test. In this way, the combinational functions of the semiconductor devices are tested at the system operating speed.

Abstract: A "personality" card (bias adapter board) is employed to program power supply connections in a DUT (Device Under Test) fixture in an automated test environment. The DUT fixture is designed to provide access to power supply voltages from the automated test equipment (ATE) and to selected (configurable) pins of the device under test. Specific connections are established between designated power supply pins of the DUT and the ATE via the bias adapter card, thereby eliminating the need for a separate, expensive DUT board for each different DUT.

Abstract: The present invention relates to a method of and system for reducing the drive requirements for the input and output pads of an integrated circuit die. An intermediate structure is added between the output connection pad and substrate to reduce the amount of electron charge required to charge the output pad capacitance to a substantially negligible amount. In addition, an intermediate structure may be added between an input connection pad and substrate to reduce the amount of electron charge required to charge the input pad capacitance to a substantially negligible amount. The present invention connects a transistor amplifier driver to the intermediate structure between the output pad and substrate to charge the capacitance that exists between the intermediate structure and substrate so that the voltage potential of the intermediate structure is substantially the same value as the output pad voltage value.

Abstract: Various forms of micromachined electrostatic microconveyors and useful devices based thereon are described. In one embodiment, a tube shaped conveyor is formed by disposing conductors circumferentially about the exterior surface of the tube. The tube is formed of an insulating material (e.g., silicon dioxide). Driving voltages are applied in staggered phase to selected ones of the conductors to provide a travelling electrostatic wave within the tube. Charged particles (or fluid or gas) can be propelled through the tube electrostatically by "riding" the travelling wave. Various aspects of the invention are directed to apparatus making use of the microconveyor to convey particles, gas ions, etc.. Apparatus is described for using gas pressure resulting from the transport of gas ions to do mechanical work (i.e., to operate mechanical actuators.

Abstract: A process of interconnecting a semiconductor device to a substrate wherein solder balls on the semiconductor device are fused with one side of an embedded noble metal foil within a through hole in an interposer structure. Solder balls on the substrate are fused with the metal foil within the structure window on the other side of the metal foil.

Abstract: Improved thermal characteristics are obtained in a multi-layer substrate for mounting a semiconductor device. A prepeg layer disposed in close proximity to or immediately adjacent to a semiconductor device is formed incorporating an integral, thermally-conductive mesh or screen. The prepeg layer is preferably a sandwich structure of two BT-resin layers (films), between which is disposed a copper screen. In this manner, heat is conducted away from an operating device by an integral part of the substrate, without the need for additional slugs or heat sink structures. Utility for multichip modules is also disclosed.