Abstract: Various forms of micromachined electrostatic microconveyors and useful devices based thereon are described. In one embodiment, a tube shaped conveyor is formed by disposing conductors circumferentially about the exterior surface of the tube. The tube is formed of an insulating material (e.g., silicon dioxide). Driving voltages are applied in staggered phase to selected ones of the conductors to provide a travelling electrostatic wave within the tube. Charged particles (or fluid or gas) can be propelled through the tube electrostatically by "riding" the travelling wave. Various aspects of the invention are directed to apparatus making use of the microconveyor to convey particles, gas ions, etc. Apparatus is described for using gas pressure resulting from the transport of gas ions to do mechanical work (i.e., to operate mechanical actuators.

Abstract: An electronic system utilizing at least one integrated circuit including a semiconductor integrated circuit chip housed in a package providing external electrical connections for the circuit chip. The system package has only a limited number of external connections available for such use. The system package includes an internal buss, or plurality of busses, which are electrically connected to the circuit chip and to selected external connections or the package to improve the efficiency of utilization of external connections on the package, as well as improving operating characteristics of the integrated circuit chip by improvements to voltage and current distributions to the chip, and also eliminating in some cases the consequences of a poor quality of external electrical connection to the system package itself.

Abstract: Electronic systems using separate and distinct conductive layers for power and ground are insulated from one another and a patterned signal conductive layer to form a flexible substrate for mounting a semiconductor die in a semiconductor device assembly of the system. TAB technology is utilized to produce an assembly that has superior electrical characteristics because power and ground is conducted on separate low impedance conductive layers. The power and ground leads connecting the semiconductor die and external circuits are selected from the signal trace layer, cut bent downward and attached by bonding to the respective power or ground layer. A tool is disclosed for cutting the selected leads. The present invention further provides a system utilizing a wafer probe card which includes a multi-layer, relatively flexible tape-like substrate having a first conductive layer patterned to have a number of probe leads thereon.

Abstract: A semiconductor device package containing a semiconductor die uses a platform mounted on an active face of the die. The platform electrically connects to at least one bond pad on the die. A package lid electrically connects to the platform on the die and a package case connection. The package case connection is also electrically connected to at least one external connector on the package. The platform and package lid thereby connect the at least one bond pad on the die to the at least one external connector on the package. Using the platform and lid for electrical connections from the semiconductor die bond pads to the external package connector reduce the number of bond fingers required to surround the perimeter of the die. The package lid and platform may, for example, be used for ground or power connections to the die bond pads.

Abstract: A self-aligning, anti-cross threading fastener having first and/or second members with lead threads having a curved surface feature from the minor diameter to the major diameter which allows the surface of the lead threads to cam over the mating threads of the other member and thereby aligning collinearly the longitudinal axis of the two members. The initial presentation angle of the two threaded members may be restricted and therefore enhanced by providing a protruding diameter feature.

Abstract: An electronic system having improved thermal transfer from a semiconductor die in a semiconductor device assembly (package) by at least partially filling a cavity in the package with a thermally conductive fluid, immersing a heat collecting portion of a heat pipe assembly into the fluid, and sealing the cavity. In order that the thermally conductive fluid does not chemically attack the die or its electrical connections, the die and connections can be completely covered with an encapsulating coating of an inorganic dielectric material, such as silicon dioxide, by any of a variety of techniques. The heat pipe provides highly efficient heat transfer from within the package to an external heat sink by means of an evaporation-condensation cooling cycle. The optional dielectric coating over the die permits selection of the thermally conductive fluid from a wider range of fluids by isolating the die and its electrical connections from direct contact with the fluid.

Abstract: Electronic systems utilizing a plurality of integrated circuit packages having a stackable heat sink assembly is formed by press-fit assembly of two or more identical fin layers. Each fin layer is formed using powdered metallurgy and has a button-like projection extending from its bottom surface and a recess opening in its top surface. The button-like projection and recess opening are sized and shaped such that an interference fit is formed when the buttonlike projection of one fin layer is pressed into the recess of another fin layer. The use of an adaptor to increase or decrease the effective size of the button-like projection of the bottom-most fin layer is described. Relieving gases that may be entrapped in the recess during assembly is described. Circular, elliptical and polygonal shapes (outlines) for the fin layers are described.

Abstract: An electronic system utilizing at least one semiconductor die having raised conductive bumps on its surface for connecting to other devices or systems is disposed on a face of a preformed planar structure (interposer) having through holes. Solder joints with conductive bumps on an underlying substrate are formed in the through holes. In one embodiment, the interposer is dissolvable. In another embodiment, the through holes are at least partially filled with a conductive material for electrically connecting to the die. In another embodiment, the through holes are angled so that the interposer acts as a pitch spreader or adapter. In another embodiment, ball bumps are disposed on a side of the interposer away from the die. In the electronic system, a semiconductor die may be disposed on a side of an optically transmissive preformed planar structure (interposer), and an optical element is disposed on an opposite side of the interposer.

Abstract: A digital system utilizing at least one semiconductor integrated circuit die having positive mechanical alignment is provided between substrates using micro-bump contacts by forming "detented" conductive bump contacts on one substrate having a concave end which receive and align the generally convex contour of bump contacts on the other substrate. Various configurations of concavities and convexities are described. Flux may be disposed in the concave end of the detented bump contact to promote formation of joints between the concave and convex bump contacts. Both bump contacts may be formed of reflowable material, such as solder, or one or the other of the contacts may be formed of a non-reflowable material which may also function as a standoff between the two substrates. Each substrate is provided with a plurality of bump contacts, and one substrate may be provided with a combination of convex and concave bump contacts corresponding to concave and convex bump contacts on the other substrate.

Abstract: Techniques for computing power and delay values for macrocells in an ASIC design are described whereby the power or delay values are encoded as a multi-dimensional mathematical expression relating the power or delay value to the values of a plurality of operating conditions. The mathematical expression is derived from a multiple regression analysis of a plurality of power or delay sample values determined for a plurality of specific operating conditions. Delay values are derived directly from the mathematical relationship. Power dissipation values are determined by encoding current draw as a function of the various operating conditions. When a predicted current draw value is computed, it is multiplied by a value of power supply voltage to determine power dissipation.

Abstract: Techniques for providing semiconductor packages capable of forming connections to "high I/O" semiconductor dies is described, wherein there are at least two distinct pluralities of conductive lines. Leadframe-type packages and substrate-based package embodiments are described.

Abstract: A differential delay buffer includes a variable delay buffer unit, the variable delay buffer unit having a differential stage followed by a variable hysteresis stage. A plurality of variable delay buffer units can be cascaded together, in each variable delay buffer units a part of the required delay being effected. The variable hysteresis stage is responsive to the signal level at a second differential stage output to recover the signal at a first differential signal output from the variable delay buffer unit and is responsive to the signal level at a first differential stage output to recover the signal at the second delayed differential signal output for the variable delay buffer unit. The differential delay buffer can be included in a delay locked loop in data transmission applications.

Abstract: Electronic systems utilizing a plurality of integrated circuit packages having at least some large gaps between edges of a semiconductor die and the inner ends of package conductors defining a die-receiving area, one or more bond wire support structure are disposed in the gap, thereby causing a long bond wire to behave as two or more shorter bond wires. The bond wires are tacked to a top surface of the support structure by various alternative means. Alternatively, a "jumper" structure having conductive traces of graduated length can be disposed in the die-receiving area between the die and the edges of the die-receiving area, providing an intermediate connection between the die and the leads of the package, thereby permitting short bond wires to be used in lieu of long bond wires.

Abstract: Electronic systems using certain non-square dies, such as triangular dies, greatly elongated rectangular dies, parallelogram dies, trapezoidal, and the like, are able to be laid out in the area of a circular semiconductor wafer more "efficiently" than square dies. Further, a peripheral area of these certain non-square dies is advantageously increased relative to the area contained within the peripheral area, to accommodate increased I/O connections to the active elements of the die.

Abstract: A greater lead count for a given die area can be achieved with "certain non-square" geometries formed by the inner ends of conductive lines. These include various triangular configurations, as well as "greatly elongated" rectangular, parallelogram and trapezoidal configurations. The conductive lines may be leads of a lead frame, leads on a tape-based package, or traces on ceramic or PCB-substrate packages. The package body may be formed to have a shape similar to that of the die receiving area, and may also be provided with external pins, ball bumps or leads. A number of these "certain non-square" packages may be assembled in an electronic system on a mother board. Unpackaged "certain non-square" dies may be connected to the ends of traces on a substrate, and encapsulated to form a multi-chip module.

Abstract: Substrates having a wide range of thickness, and intended to be overmolded with a plastic package body, are accommodated in a common mold. The top surface of the substrate is provided with a dam structure, which may be formed as an additional layer on the substrate, and which is preferably in the form of a square ring. A groove (channel) is machined (e.g., by routing) into the surface of the dam structure. The top mold half, having a cavity for forming the package body, is provided with a sealing structure at the periphery of the cavity. The sealing structure has a ridge fitting into the channel of the dam structure. The depth of the groove in the dam structure is readily adjusted to ensure uniform clamping pressure of the top mold half on the substrate, so that liquid molding compound is contained within the cavity and so that undue pressure is not exerted on the substrate.

Abstract: System for producing a plurality of semiconductor device assemblies utilizing a grid array of conductive epoxy for connecting them to an electronic system. Conductive epoxy is screen printed in a desired pattern onto a printed wire board of the semiconductor device assembly. The conductive epoxy is B-staged by heating in an oven. The semiconductor device assembly is then placed onto a system printed circuit board wherein the B-staged conductive epoxy is further cured by heat and effectively makes mechanical and electrical connections between the semiconductor device assembly and the system printed circuit board.

Abstract: A semiconductor device assembly having external connections, including power supply connections such as to a power source or ground, is made without resort to bond fingers. Rather, external connections are directly made from a semiconductor die to a conductive layer. The conductive layer is disposed on one surface of a printed wring board and is divided into electrically insulated conductive segments. Each of the conductive segments is connected to an external connection, and includes one or more interconnects that can be directly connected to a semiconductor die. The conductive segments are surrounded by an array of bond fingers which serve to connect the semiconductor die to further external connections, such as signal connections. The present invention is especially advantageous in the fabrication of pin grid array (PGA) and ball grid array (BGA) type integrated circuit packages.

Abstract: A thermal management structure to provide mechanical isolation and heat removal for a unpackaged semiconductor die mounted directly on a printed circuit board substrate. The thermal management structure sandwiches the unpackaged semiconductor die and substrate between two heat sink pieces which are rigidly mounted to the substrate, thereby mechanically isolating the unpackaged semiconductor die and preventing the die from being accidentally touched. The two heat sink pieces further compliantly thermally engage selected sites on the exposed face of the semiconductor die and the surface of the substrate to conductively remove heat away from the substrate. The thermal management structure may also thermally engage selected thermally conductive components within an end product to spread the heat more uniformly throughout the system.

Abstract: An electronic system having optical elements in association with photosensitive elements is described. In some of the arrangements, the optical elements are formed integrally with a substrate containing the photosensitive elements. In other arrangements, an optical element is mounted to a package, or the like, containing the substrate and photosensitive elements. In other arrangements, two or more optical elements are employed, including conventional refractive elements, refractive focusing elements, and refractive beam splitting elements. Utility as solid state image sensors is discussed. Utility for monochromatic and color imaging is discussed. Various devices based on such camera arrangements and methods of making same are discussed.