Abstract: Sensing a gas includes introducing a gas into a chamber, forming a standing acoustic wave in the chamber, and irradiating the chamber with electromagnetic radiation. Some of the electromagnetic radiation passes into the chamber, through the standing acoustic wave in the chamber, and out of the chamber. An amount of electromagnetic radiation that passes out of the chamber, or is transmitted through the chamber, is detected. A concentration of the gas in the chamber can be assessed.

Abstract: Very low loading of impact modifier less than 4% can significantly improve elongation and impact strength of N6/clay nanocomposites and keep the high tensile strength and modulus. This rubber modified nylon nanocomposites have potential applications in fabricating high-strength fibers for textile industry, coatings for strings or polymer parts, and packaging industry.

Abstract: When a flash unlock routine unlocks the flash memory to permit updating of a BIOS image, a message is left in secure non-volatile memory, such as a EEPROM. Upon the next re-boot, the boot block code will detect the special message in the non-volatile memory and perform a signature verification of the next block of code that is to be executed during the POST process. This code block will check the remainder of the BIOS image before POST proceeds.

Abstract: Presented is a “high-order” Leading Zeros Anticipator or LZA circuit and specifically a five-input LZA. The prior-art two-input LZA circuit is part of almost all high-performance floating-point units or FPUs. The advantages of a high-order LZA (such as five-input) is that the LZA function may be started and finished sooner in the floating point pipeline, and therefore allows more time for other functions in the pipeline. Therefore, a high-order LZA, such as five-input LZA, may be faster than the prior art two-input LZA designs. Thus, speeding up the LZA function in a floating point pipeline may significantly increase the speed in which the overall floating-point unit may operate as compared to the prior-art two input LZA designs and may additionally inspire new floating-point michroarchitectures which may yield further performance gains.

Abstract: A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor.

Abstract: An automated third party verification system and method for verifying a customer's authorization to switch long distance service providers. The system broadly comprises a customer database manager, a third party verification (TPV) interactive voice response (IVR) system, and a TPV management system. The customer database manager contacts the customer and, responsive to the customer's authorization to switch long distance carriers, creates a text file of the customer's responses to a series of questions supporting the authorization. The text file is sent to the TPV IVR system. The TPV IVR system directs a series of scripted questions, corresponding to those already asked by the customer database manager, to the customer and records the responses as voice clips. The TPV management system presents the voice clips and the corresponding text file to a verifier through a voice data verification module.

Abstract: Accordingly, a digital logic circuit in the form of a finite state machine (FSM) is implemented in a semiconductor structure such as complementary metal oxide silicon (CMOS) with reduced power dissipation by determining transition probabilities for transitions between states in the FSM, producing a constraint matrix to identify constraints to producing a minimum area implementation consistent with minimum power dissipation, constructing one or more state chains having transitions with highest probability and implementing each of these state chains in order of probability to achieve the implementation of the FSM having minimum power dissipation.