Abstract: A signal isolator comprises an isolation barrier, a transmitter, a differentiator, and a recovery circuit. The transmitter is coupled to a first side of the isolation barrier and is configured to receive and convert an information signal to a differential signal that encodes information in the information signal in a single transition edge. The differentiator is coupled to a second side that is isolated from the first side of the isolation harrier and differentiates the differential signal. The recovery circuit is coupled to the differentiator and operates to recover an output information signal based on the information in the single transition edge.

Abstract: A supersonic aircraft comprises a wing having upper and lower surfaces and extending from a leading edge to a trailing edge and at least two engine nacelles coupled to the lower surface of the wing on the trailing edge. The supersonic aircraft further comprises an inverted V-tail abutting to the upper side of the wing comprising a central vertical stabilizer, at least two inverted stabilizers coupled to sides of the central vertical stabilizer and coupled to the wing and supporting at least two engine nacelles, and at least two ruddervators respectively pivotally coupled to at least two inverted stabilizers. The supersonic aircraft also comprises a controller coupled to at least two ruddervators and capable of adjusting the aircraft longitudinal lift distribution throughout a flight envelope to maintain a reduced sonic boom and reduced drag trim condition.

Abstract: An optical sensor includes an optical source capable of being positioned on a tissue and emitting near infrared light into the tissue at a plurality of selected wavelengths, and a photodetector capable of detecting reflected light from the tissue. The photodetector being positioned on the tissue removed from the optical source but sufficiently close in proximity to the optical source to contact the same general tissue. The optical sensor further includes an oscillator coupled to the optical source and capable of activating the optical source to emit the near infrared light, and a modulator coupled to the oscillator and capable of controlling radio frequency modulation of the optical source to emit a radio frequency component that is used to measure the optical path length and absorbance of an analyte of interest within the tissue.

Abstract: A family of interconnect structures, switches that exploit the interconnect structures to attain scalability, low latency, and single-chip implementations. The disclosed interconnect structures and switches support a wide variety of applications including supercomputer interconnects, LAN switches, IP and ATM switches, telephony central office switching, video on demand servers, interconnects for mainframe database servers, high-speed workstation interconnects, and many others that are known to those having ordinary skill in the art.

Abstract: A diagnostic apparatus includes a near infrared spectrophotometer (NIRS) and an ultrasound transducer that operate in combination to improve diagnostic measurements. The diagnostic apparatus includes a near infrared spectrophotometer that measures an analyte, for example tissue oxygenation, in an optical sample volume and an ultrasound imager to accurately position the optical sample volume in biological tissue or vessels. In one example, the diagnostic apparatus includes an optical source, a linear array of ultrasound transducers, and an optical photodetector arranged in the same plane so that the ultrasound sample volume interrogated by the ultrasound transducers intersects the optical sample volume formed by the optical source and detector.

Abstract: A health care test kiosk includes a carrel body that supports a console housing and has a vacant knee-space beneath the console housing. The carrel body includes a support side panel forming a lateral side and extending beyond the console housing and the knee-space. A physiological test interface is connected to and supported by the carrel body on the support side panel. A retractable seat is movably connected to the support side panel of the carrel body for selective positioning in a location ranging from withdrawn into the knee-space beneath the console housing to extended completely from the knee-space.

Abstract: A processor includes a “four-dimensional” register structure in which register file structures are replicated by N for vertical threading in combination with a three-dimensional storage circuit. The multi-dimensional storage is formed by constructing a storage, such as a register file or memory, as a plurality of two-dimensional storage planes.

Abstract: A computation unit computes a division operation Y/X by determining the value of a divisor reciprocal 1/X and multiplying the reciprocal by a numerator Y. The reciprocal 1/X value is determined using a quadratic approximation having a form: Ax2+Bx+C, where coefficients A, B, and C are constants that are stored in a storage or memory such as a read-only memory (ROM). The bit length of the coefficients determines the error in a final result. Storage size is reduced through use of “least mean square error”techniques in the determination of the coefficients that are stored in the coefficient storage. During the generation of partial products x2, Ax2, and Bx, the process of rounding is eliminated, thereby reducing the computational logic to implement the division functionality.

Abstract: A multi-ported register file is typically metal limited to the area consumed by the circuit proportional with the square of the number of ports. A processor having a register file structure divided into a plurality of separate and independent register files forms a layout structure with an improved layout efficiency. The read ports of the total register file structure are allocated among the separate and individual register files. Each of the separate and individual register files has write ports that correspond to the total number of write ports in the total register file structure. Writes are fully broadcast so that all of the separate and individual register files are coherent.

Abstract: A parallel fixed-point square root and reciprocal square root computation uses the same coefficient tables as the floating point square root and reciprocal square root computation by converting the fixed-point numbers into a floating-point structure with a leading implicit 1. The value of a number X is stored as two fixed-point numbers. In one embodiment, the fixed-point numbers are converted to the special floating-point structure using a leading zero detector and a shifter. Following the square root computation or the reciprocal square root computation, the floating point result is shifted back into the two-entry fixed-point format. The shift count is determined by the number of leaded zeros detected during the conversion from fixed-point to floating-point format.

Abstract: A processor includes a thread switching control logic that performs a fast thread-switching operation in response to an L1 cache miss stall. The fast thread-switching operation implements one or more of several thread-switching methods. A first thread-switching operation is “oblivious” thread-switching for every N cycle in which the individual flip-flops locally determine a thread-switch without notification of stalling. The oblivious technique avoids usage of an extra global interconnection between threads for thread selection. A second thread-switching operation is “semi-oblivious” thread-switching for use with an existing “pipeline stall” signal (if any). The pipeline stall signal operates in two capacities, first as a notification of a pipeline stall, and second as a thread select signal between threads so that, again, usage of an extra global interconnection between threads for thread selection is avoided.

Abstract: A method and computer system for a system setup program includes a routine for displaying a subset of bootable devices from an adapter card, such as a PERC card, on a system from which a user may specify a bootable device to serve as a boot drive, and bootable devices to serve as alternative boot drives. The computer system includes a system Basic Input/Output System (BIOS), a system processor, a system memory coupled to the system processor, at least one expansion slot coupled to the system processor via a bus, at least one adapter coupled to the computer system via the at least one expansion slot, and a system BIOS ROM code. The BIOS ROM code detects a plurality of bootable devices on the computer system, selects from the plurality of bootable devices a preselected number of bootable devices for display, and displays the subset of bootable devices on a setup display. The setup display allows a user to specify a bootable device to serve as a boot drive of the computer system.

Abstract: A scalable low-latency switch extends the functionality of a multiple level minimum logic interconnect structure for usage in computers of all types, networks and communication systems. The multiple level minimum logic interconnect structure employs a data flow technique based on timing and positioning of messages moving through the structure. The scalable low-latency switch is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided while the interconnect structure operates as a “deflection” or “hot potato” system in which processing and storage overhead at each node is reduced. The interconnect structure using the scalable low-latency switch employs a method of achieving wormhole routing through an integrated circuit chip by a novel procedure for inserting messages into the chip.

Abstract: Adapter cards generally have a metal bracket at one end. The adapter card attaches to an adapter card slot of a computer system by fastening the bracket to a connector on the computer system. Conventionally, the bracket is fastened to the connector using a screw. It has been discovered that an electrically-conductive flip-down retainer advantageously functions as an improved fastener to secure the adapter card to the connector. The electrically-conductive flip-down retainer is a single structure that performs the combined functions of an electrical switch and a mechanical fastener. The electrically-conductive flip-down retainer includes electrical contacts that form a closed circuit when the bracket is fastened to the connector and an open circuit when the bracket is not fastened. The electrical contacts are connected to conductors extending to a controller.

Abstract: A computing system and operating method are executable on a target processor and bootstrap loads and run an application program or interface from an alternative medium, for example a CD-ROM medium or via a network link, when an operating system associated with the application program or interface is not installed on the target processor. For example, a computing system includes an executable program code or command entries that load and run a graphical user interface functionality when the operating system associated with the graphical user interface is not installed. The computing system typically includes a processor, a CD-ROM drive coupled to the processor, and a Random-Access Memory (RAM) Drive coupled to the processor. The executable program code or command entries substitute a designator of the RAM-Drive in place of predefined drive designators that are hard-coded into base code of the operating system.

Abstract: A processor implements a local stall functionality in which small, independent circuit units are stalled locally with the condition causing a stall being first detected locally, then propagated to other small independent circuit units. Stall conditions for a functional unit are detected locally with reduced logic circuitry and also without waiting to receive condition information from other functional units that is transmitted over long wires. Local stall logic circuits are distributed over diverse areas of an integrated circuit so that stall conditions are detected locally. A local stall is expanded into a global stall by propagation to logic circuits beyond a local region in subsequent cycles. Local detection of stall conditions and local stalling eliminates many critical paths in the processor.

Abstract: A network or interconnect structure utilizes a data flow technique that is based on timing and positioning of messages communicating through the interconnect structure. Switching control is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided. The interconnect structure operates as a “deflection” or “hot potato” system in which processing and storage overhead at each node is minimized. Elimination of a global controller and buffering at the nodes greatly reduces the amount of control and logic structures in the interconnect structure, simplifying overall control components and network interconnect components and improving speed performance of message communication.

Abstract: A process controller implements and executes a standard set of function blocks or control functions defined by a standard protocol so that standard-type control is achieved with respect to non-standard-type devices. The process controller enables standard devices to implement the standard set of function blocks and control functions. The process controller implements an overall strategy as if all connected devices are standard devices by usage of a Fieldbus function block as a fundamental building block for control structures. These function blocks are defined to create control structures for all types of devices.

Abstract: An Advanced Process Control (APC) Framework performs automatic process control operations through the design and development of a software framework that integrates factory, process, and equipment control systems. The APC Framework benefits semiconductor-manufacturing factories, or “fabs,” throughout the development of the APC Framework by using an iterative development approach. The APC Framework is designed to integrate seamlessly with commercially-available APC tools. The APC Framework specifies components and a component structure that enable multiple vendors to build and sell framework-compatible products using an open architecture that accommodates plug-and-play components. The APC Framework advantageously increases product yield distributions and equipment utilization, and lowers defect densities.

Abstract: A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are electrically isolated from one another by means of a gate insulating layer that is formed adjacent the side-walls of each firs gate electrode. Source and drain regions are formed adjacent the ends of the multiple split gate to define a channel region.