Abstract: A tristate driver interfaces a 3.3 volt digital circuit to a bus that supports both 3.3 and 5.0 volt digital signals. In one embodiment, the pullup circuit path includes a P-channel MOSFET which is backgated by a backgate voltage generator and gated by a gate voltage generator that receives its drive voltage from a comparator and is controlled by an enable circuit. The pulldown circuit path includes an N-channel MOSFET which is controlled by the enable circuit. Current leakage through the pullup circuit is minimized when overvoltage occurs on the bus by suitably gating and backgating the pullup MOSFET. In another embodiment, two MOSFETs are used in the pullup circuit. Both are backgated by a backgate voltage generator, while one is gated by a gate voltage generator that receives its drive voltage from the bus while the other is controlled by an enable circuit. The pulldown circuit path includes an N-channel MOSFET which is controlled by the enable circuit.

Abstract: A complementary transistor class AB output stage (200) utilizes a complementary pair of output drivers (220, 222) connected in series between the power supply rails (210, 216) to furnish the stage output. An output driver (206) is a composite pair of transistors in a Darlington configuration, which boosts the current gain and input resistance of the output stage. Bases of the output drivers are connected by a complementary pair of parallel connected drivers (226, 228), which function as common base level shifters. Quiescent bias of the output drivers is achieved by a pair of constant current transistors (232, 238) that are operated as complementary current mirrors. Inputs to the mirrors are relatively low current sink (252) and source (250) supplies.

Abstract: A voltage translator is provided that translates a lower voltage to a higher voltage, for example, a 3.3 V voltage to a 5.0 V voltage. The 3.3 V voltage is received on source/drain terminal N1 of an NMOS transistor. The transistor gate is at 3.3 V. The other source/drain terminal N2 of the transistor is connected to an input of a CMOS inverter powered by 5.0 V. The inverter output is connected to the gate of a PMOS transistor connected between 5.0 V and terminal N2. The PMOS transistor pulls terminal N2 to 5.0 V when terminal N1 is at 3.3 V. The same translator is suitable for translating a 5.0 V voltage on terminal N1 to 3.3 V on terminal N2 if the inverter is powered by 3.3 V and the PMOS transistor is connected between 3.3 V and terminal N2. Also, an output driver is provided in which a voltage protection circuitry prevents charge leakage from the driver output terminal to the driver's power supply when the voltage on the bus connected to the output terminal exceeds the power supply voltage.