Abstract: An innput/output terminal assembly for pressure transducers of the flexure type. The transducer includes a flexure member which senses an applied pressure by means of strain gauges mounted thereon. A known problem with such an arrangement concerns the electrical connections to the strain gauges wherein there is conflict between the flexible connections required to accommodate flexure displacement and the rigid connections required to lead away from the gauges since a pressure chamber must be spanned. Previously this conflict has been resolved by bonding an insulative terminal plate proximate the flexure to provide a junction between flexible and rigid conductors. Such an arrangement gives rise to problems of construction rigidity and performance if excess bonding resin contacts the flexure. The invention provides a welded terminal plate, which is insulative by virtue of a thick film layer of glass, on which electrical connection may be made to areas of thick film gold.

Abstract: A CMOS buffer for the dynamic translation of input signals at TTL levels to corresponding signals at CMOS levels. A reference voltage at a level between the 0.8 volt maximum TTL "0" input level and the 2.4 volt minimum "1" input level is generated by charge distribution between capacitors. This reference level is compared with an input signal level in a dynamic comparator comprised of a CMOS cross-coupled latch to produce output signals at CMOS levels that correspond to the TTL input signals.

Abstract: A self-refreshing non-volatile memory cell having two cross-coupled transistors includes a first floating gate formed between the gate and the channel of said first transistor, said first floating gate overlying by means of a tunnel oxide a portion of the drain of said second transistor and a second floating gate formed between the gate and channel of said second transistor, a portion of said second floating gate overlying by tunnel oxide a portion of the drain of the first transistor. Disturbances in the supply voltage and the gate voltage of the device normally enhance rather than degrade the state of data stored in the cell, thereby providing an extremely long storage time for the cell. The cell is capable of operating simultaneously in a volatile and a non-volatile state.

Abstract: A method and circuitry are disclosed for correcting bit errors introduced by random events in a data recirculating memory, such as a charge coupled memory device or a bubble memory. The bit errors, caused by random events such as by alpha particle bombardment or other causes, are corrected in circuitry that generates row and column parity bits corresponding to various segments of the information stored in the memory. Changes in the row and column parity bits uniquely define the location of failed bits circulating through the memory even though each failed bit has no fixed address, so that error detection circuitry thereafter may correct the error during the next or a subsequent bit recirculating cycle. The invention facilitates the use of very large memories, for example, on the order of one billion bits or more.

Abstract: A low temperature LPCVD process for co-depositing metal and silicon to form metal silicide on a surface such as the surface of a semiconductor integrated circuit wherein the metal is selected from the group consisting of tungsten, molybdenum, tantalum and niobium. A reactor which contains the surface is maintained at a temperature of about 500.degree.-700.degree. C. The reactor is purged by the successive steps of introducing an inert gas into the reactor, introducing a reducing atmosphere into the reactor and introducing hydrogen chloride gas into the reactor. Silane is then introduced into the reactor such that a base layer of polysilicon is formed on the surface. Then, while maintaining silane introduction to the reactor, metal chloride vapor is simultaneously introduced into the reactor such that metal and silicon are co-deposited on the polysilicon as metal silicide.