Abstract: Circuitry, including a non-volatile dynamic random access memory cell, a sense amplifier and a data latch affords non-destructive accessing and comparison of the data stored within the volatile and non-volatile portion of the memory cell. In certain applications, it is desirable to restore the volatile data to the volatile portion of the memory cell, and the circuitry also provides a path for such restoration.
Abstract: An operational amplifier suitable for inclusion in an integrated circuit device operating as a transceiver at a coaxial media interface to a network meeting IEEE 802.3 standards. To be included in an integrated circuit package the operational amplifier must have low-power consumption and yet generate up to 80 mA of current onto the network. A design method achieves this goal, producing an operational amplifier having three independently-positioned, isolated, poles. A current generator and level shifter is employed with the operational amplifier which generates a current precisely proportional to a "collision" reference voltage, the current is compensated for changes in temperature and for variations in transistor gain (hFE). A very wide band level shifter matches the current generated to the requirements of the operational amplifier so that 10% to 90% changes in current generated by the op amp can occur in 1/2 to 3/4 of a nanosecond, yet the level shifter does not consume much power.
Abstract: An apparatus and process employing an integrated circuit device technology within a linear feedback shift register using a cyclic redundancy check code scheme for validating the device technology under realistic very large scale integrated circuit operating conditions. By deploying two feedback shift registers in a full-duplex mode, the device technology can be subjected to arbitrarily-long, pseudo-random test signal sequences. Also, by checking the registers with variable-phase pulses, representative device delay time information can be obtained.
Abstract: A memory cell providing separate storage of volatile and non-volatile data. The volatile and non-volatile data elements, which are not necessarily duplicative, can be non-destructively accessed within a single memory clock cycle via separate volatile and non-volatile bit lines. The cell stores volatile data by the storage of charge on a dynamic storage capacitor formed of a semiconductor device and stores non-volatile data by the storage of charge in the floating gate of a transistor. An array of the memory cells illustrates comparison of the volatile and non-volatile data elements within a single memory cycle particularly suited for pattern recognition.
Abstract: A method and device for adapting the scanning-resolution used by a first document-scanning device acting as an input device to a scanning-resolution used by a second such device acting as an output device so that the signals generated by the first device can be processed by the second device. User-selectable input and output scanning resolutions determine an output/input resolution ratio which specifies replication of scan-lines received from the input device and transmittal and skipping of selected ones of these scan-lines to the output device. Replication and skipping of scan-lines take place concurrently so that only a single scan-line need be accessed and stored during the adaption resolution process. The method and apparatus of the present invention permit connection of an input scanning device to an output scanning device without restriction as to the scanning-resolutions used internally within the devices.
Abstract: A monolithic integrated circuit chip preferably includes a pair of data busses capable of conducting in parallel the number of signals which can be processed simultaneously by the components on the chip. Signals on the busses are carried in a time-multiplexed manner, each bus having a predetermined number of time slots. Preferably, each component on the chip is connected to one or both of the busses and is assigned a particular time slot for the bus to which it is connected. The resulting chip is of a structured, rather than a custom, design. Accordingly, it can be readily expanded or contracted in the number of signals which can be simultaneously processed. The number of components which can be included on the chip is limited only by the number of time slots available on the bus to which it is connected. By providing two busses, such common circuit elements as two-input adder/subtractors can be readily accommodated by a chip designed according to the instant invention.
August 30, 1985
Date of Patent:
February 3, 1987
Advanced Micro Devices, Inc.
Ronald C. Laugesen, Padmanabha I. Venkitakrishnan
Abstract: A CPU data path portion having an ALU, an adjuster unit, a shifter unit and a shift register unit is disclosed. The CPU is capable of selectively forming the sum or difference of a first BCD operand and a second BCD operand by arithmetically combining the operands with the ALU to form binary results, the results dependent upon the arithmetic operation selected and adjusting the results with the adjuster unit into BCD, the adjustment also dependent upon the arithmetic operation selected. The CPU is further capable of selectively converting an operand from binary to BCD format or from BCD to binary format by iteratively shifting the operand between the shifter unit and the shift register unit and correcting the operand with the ALU, the direction of the shift and the ALU correction dependent upon the conversion selected.
Abstract: A digital subscriber controller having a number of analog ports and digital ports which can be programmed via an external microprocessor to establish time-division multiplexed bidirectional data paths between three subscriber-selected ports designated as "sources" and three subscriber-selected ports designated as "destinations". Among the ports is a line-interface port having two 64 kilobit-per-second voice/data channels and a 16 kilobit-per-second data control channel. Among the digital ports is a three-channel serial interface port and a two-channel microprocessor interface port. An analog port is also provided at which a variety of audio transducers may be connected. The controller includes a line interface unit, a data link controller which processes data channel information present at the line interface unit, a main audio processor, a microprocessor interface, and a multiplexer which establishes the data paths selected by the subscriber.
July 26, 1985
Date of Patent:
January 6, 1987
Advanced Micro Devices, Inc.
Alan T. Clark, Hadi Ibrahim, Arthur F. Lange
Abstract: A single-array memory employs a novel storage cell providing dual read/write access via either an "A"-side or a "B"-side. The storage cell uses a unique circuit in which read current is borrowed during writing into the cell. Asymmetrical read/write delay circuitry is provided to avoid overwriting the contents of a storage cell during the read-to-write transition. Row-selection decoders use Schottky-clamping diodes in a way which provide an equivalent oscillation-damping capacitance at the base of the selected-row driver transistor. The single-array memory can be advantageously used as part of a single-chip VLSI four-port register file permitting simultaneous reading and/or writing of registers from any of two read ports or two write ports, respectively. Unidirectional busses connect each storage cell to each of the four ports.
Abstract: A two read-port, two write-port register file on a single integrated circuit chip provides dual read/write access via either an "A"-side or a "B"-side of a single array of addressable registers. Separate on-chip "A"-side and "B"-side multiplexers permit reading or writing of an independently addressed register according to the phase of the "A"-side or "B"-side clock. Writing can be selectively effected to either a high-order and/or a low-order byte within the addressed register. Unidirectional busses connect each register to each of the four ports. The register can be expanded to provide a four read-port, two write-port register file such as is required for the parallel computation of addresses and data.
Abstract: A method for rapidly recovering the clock from Manchester-encoded signals using simple digital techniques is provided for use in an inexpensive Manchester-encoding receiver. The received Manchester-encoded signal is monitored to determine zero-voltage crossing. At each such crossing the frequency of the recovered clock is adjusted by comparing the occurrence of the zero-crossing with respect to the midpoint of the period of the presently-generated recovered clock. Shorten, center or lengthen adjustment signals are generated as a result of this comparison which are used to shorten or lengthen, by 1/16 increments of the inter-bit period of the received data signal, the period of the next-generated recovered-clock. The method is readily implemented as a sixteen-stage programmable counter providing a phase-locked loop.
Abstract: A signal pre-processing method for detecting valid Manchester-encoded activity on a line carrying Manchester-encoded data signals to an inexpensive Manchester-decoding receiver. Detection is provided by monitoring both a positive-level presence and a negative-level presence to determine whether the received Manchester-encoded signal exceeds a predetermined positive voltage or falls below a predetermined negative voltage. Following detection of such line activity, the received signal is determined to be validly Manchester-encoded if it first crosses a predetermined positive level or a predetermined negative level after having first previously crossed the opposite level within a time interval of 3/4 to 11/4 of the inter-bit period of the received data signals.