Abstract: Polishing pads are provided having a polishing surface formed from a material. The polishing surface has a topography produced by a thermoforming process. The topography consists of large and small features that facilitate the flow of polishing fluid and facilitate smoothing and planarizing.

Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing, pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad also exhibits a stable morphology that can be reproduced easily and consistently. The pad surface has macro-texture that includes perforations as well as surface groove designs The surface groove designs have specific relationships between groove depth and overall pad thickness and groove.area and land area.

Abstract: A composition is provided in the present invention for polishing a composite semiconductor structure containing a metal layer (such as tungsten, aluminum, or copper), a barrier layer (such as tantalum, tantalum nitride, titanium, or titanium nitride), and an insulating layer (such as SiO2). The composition comprises an aqueous medium, an oxidant, an organic polymer that attenuates removal of the oxide film. The composition may optionally comprise a complexing agent and/or a dispersant.

Abstract: A method for chemical mechanical planarization of a semiconductor structure comprised of a conductive metal interconnect layer, a barrier or liner film, and an underlying dielectric layer using a two-step polishing process is provided. In the first step, the conducting metal overburden is substantially removed with little removal of the barrier or liner layer or the underlying dielectric structure. In the second step, the barrier layer is removed with little removal of the underlying dielectric layer. Five different methods and associated slurry compositions are described for the second polishing step, each adjusted to the state of the wafer following the first step of polishing. By using the appropriate method, the integrity of the remaining semiconductor structure can be substantially retained.

Abstract: A polishing pad with a polishing layer having a macro-texture and a micro-texture wherein the polishing layer is formed by solidifying a flowable material, the polishing layer further comprising hard domains and soft domains, each domain having an average size less than 100 microns.

Abstract: A stacked polishing pad includes an upper polishing layer and a lower sub-layer having major faces which are in contact with each other. The polishing layer is substantially impermeable to liquid while the sub-layer is liquid absorbent. The sub-layer has an outer peripheral edge which is sealed to prevent absorption of liquid into the sub-layer through the outer peripheral edge. When the stacked polishing pad is mounted on a platen of a polishing machine, the sub-layer has no exposed surface which can absorb liquid.

Abstract: A composition is provided in the present invention for polishing a composite semiconductor structure containing a metal layer (such as tungsten, aluminum, or copper), a barrier layer (such as tantalum, tantalum nitride, titanium, or titanium nitride), and an insulating layer (such as SiO2). The composition comprises an aqueous medium, an oxidant, an organic polymer that attenuates removal of the oxide film. The composition may optionally comprise a complexing agent and/or a dispersant.

Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.

Abstract: A dry solids composition is provided which may be reconstituted into a chemical-mechanical polishing composition comprising no abrasive particles.

Abstract: This invention is directed to a polishing composition used for the chemical mechanical polishing of semiconductor wafers having a copper metal circuit. The composition has a pH of under 5.0 and comprises the following: (a) a water soluble carboxylic acid polymer comprising polymerized unsaturated carboxylic acid monomers having a number average molecular weight of about 20,000 to 1,500,000 or blends of high and low number average molecular weight polymers of polymerized unsaturated carboxylic acid monomers; (b) 1 to 15% by weight of an oxidizing agent, (c) up to 3.0% by weight of abrasive particles, (d) 50-5,000 ppm (parts per million) of an inhibitor, (e) up to 3.0% by weight of a complexing agent, such as, malic acid, and (f) 0.1 to 5.0% by weight of organic polymer particles, wherein the polymer of the organic polymer particles has a number average molecular weight of at least 500,000 determined by GPC (gel permeation chromatography) and a Tg (glass transition temperature) of at least 25° C.

Abstract: Method for polishing the surface of a semiconductor wafer is provided in which the polishing pad has on its surface a multiplicity of abrasive particles which contact the wafer surface in combination with a reactive liquid solution essentially free of abrasive particles wherein the ionic strength of the solution is changed to effect a change in polishing.

Abstract: An apparatus and method for polishing the surface of a semiconductor wafer is provided in which the polishing pad has on its surface a multiplicity of nanoasperities which are particles having an imputed radius (of curvature) of about 0.5 to about 0.1 microns and sufficient resiliency to permanently deform by less than 10% which contact the wafer surface in combination with a reactive liquid solution which may be recirculated, analyzed, adjusted, and from which soluble reaction products may be removed.

Abstract: This invention describes improved polishing pads useful in the manufacture ofsemiconductor devices or the like. The pads of the present invention may have an advantageous hydrophilic polishing material and are sufficiently thin to generally improve predictability and polishing performance.

Abstract: A method of making a polishing pad composition comprising a high modulus phase component and a low modulus phase component, and a method of polishing a semiconductor substrate by creating nanoasperities at a polishing interface between the polishing layer and the wafer during polishing by providing the high modulus phase component at the polishing interface, either as protrusions from the polishing layer, or by being released from the polishing layer into the polishing interface.

Abstract: A method for CMP polishing with a first step slurry composition selective to a metal in a metal layer to remove the metal at a high removal rate during polishing, and a second step slurry composition selective to a barrier film and least selective to either of an underlying dielectric layer or a metal interconnection structure in the dielectric layer, to remove the barrier film at a high removal rate during polishing, and level a surface of the dielectric layer to the surface of the interconnection structure.