Abstract: Data recovery apparatus for receiving two channels of data signal portions skewed in time and recovering from them two data signal portions synchronized with a con, non clock signal. The apparatus includes a phase comparator circuit and a latch circuit associated with each channel of data signals, a single voltage controlled oscillator that generates a clock signal VCO-CLK in response to a VCO control signal and a single charge pumping circuit for generating the VCO control signal. Each phase comparator circuit receives its associated channel of data signal portions and the VCO-CLK signal and generates pump-up/pump-down signals applied to the charge pumping circuit. Each latch circuit is triggered by a selected edge of the VCO-CLK signal, so that the latch circuits respectively provide recovered data signal portions synchronized with the VCO-CLK signal, which may then be recombined in the same sequence as they were originally divided from a common high data-rate signal.

Abstract: A test fixture for facilitating connection between the test leads of a diagnostic device and a pin grid array, dispersion via, or other multi-leaded electronic components mounted on a printed circuit boards. A base is provided of a nonconductive material having holes for spring loaded test pins. In the center of the fixture is a threaded rod which attaches the fixture onto a small threaded stud attached to the printed circuit board. The screw attachment is designed so that the fixture first screws onto the metal stud with light finger pressure. A nested screw arrangement utilizing a left hand threaded part then presses the fixture against the printed circuit board, compressing the test pins for good contact.

Abstract: A communication client is connected to multiple display servers. When a client of one of the display servers issues a communication, the communication client notes the communication in the display server coupled to the client and relays the communication to the other servers for use by clients of the other servers.

Abstract: An arbitration mechanism for controlling a coupling order between a number of resources and a number of requesters having a number of requests processing units, one associated with each one of the requesters, for receiving a resource type request signal from the associated requester, a number of grant processing units, one associated with each one of the resources, for monitoring a busy status signal from said associated resource, a common broadcast medium coupled to the number of request processing units and the grant processing units, and an arbiter for granting access to said common broadcast medium to one of the request processing units and the grant processing units using the common broadcast medium to control the coupling order between the requesters and the resources in a first come, first served manner.

Abstract: A simulation method allowing an experimenter to model a real-world situation in order to learn something about it. The method permits interaction of concurrent experiments through interaction between different variables during a single simulation run on a computer having at least one central processing unit.

Abstract: A node operating in a network using the International Standard Organization (ISO) High-Level Data Link Control (HDLC) network protocol includes a mechanism for encoding information such that frames including the encoded information can be correctly interpreted by nodes operating in either of the standard 16-bit or 32-bit ISO-HDLC operating modes. The encoding mechanism produces a preliminary frame check sequence by encoding the information in an encoder using a generator polynomial G.sub.48 (x), which is a combination of the generator polynomials G.sub.16 (x) and G.sub.32 (x) which are used to produce frame check sequences for nodes operating in 16-bit or 32-bit modes, respectively. Before the information is encoded, the encoding mechanism sets the encoder to an initial condition using an initializing polynomial I.sub.48 (x). The preliminary frame check sequence is further encoded by adding to it a complementing polynomial C.sub.48 (x). The result is a 48-bit frame check sequence.

Abstract: A message switching network is disclosed which consists of end units between which messages flow. The end units are coupled together directly (via LANs) or via common switching nodes through level 0 links; the nodes are coupled together via level 1 links; and the nodes are grouped into areas which are coupled together via level 2 links. A message entering a node has its destination area code compared with the node's area code, and an area/port table or an end unit/port table is used to look up the output port which is coupled to the end unit, next node in the area, or next area to which that message is to be delivered. Logic circuitry determines the incoming and outgoing levels, and a transition between levels is logged together with certain details of the message. Messages are thus monitored--i.e., their passage is recorded--when they cross levels in the hierarchy.

Abstract: A method and apparatus for improving the performance of the transferring of transaction handshakes between sections of synchronous logic which are in different timing domains providing immunity from set-up and hold violations and associated problems of metastability, by reducing the time overhead required for signal synchronization.

Abstract: A simulation method allowing an experimenter to test and debug computer programs concurrently. The method ultilizes the generation of signatures to observe interactions of various subprogram paths with a reference case.

Abstract: The present invention includes an approach to improving run-time performance of rule-based systems. A series of testing element nodes making up a testing element is adapted to a match discrimination network utilized in an expert system to permit scanning of incoming data prior to traversing large segments of the nodes in the match discrimination network. By placing a series of testing element nodes into a traditional match discrimination network, interaction among data objects and nodes of the match discrimination network are minimized.

Abstract: A method of searching and maintaining data elements in memory which are stored in a doubly-linked list. A logically related address component array is used to access data elements in the list. The list is divided into list segments which are dynamically maintained to decrease overall access time.

Abstract: In a data processing system in which a processing unit can execute both scalar and vector instructions, the use of a single operand register file to store both the scalar operation operands and the vector operation operands is described. An instruction is included in the instruction repertoire in which a field is decremented (until a zero field is reached) to provide the next sequential operand address and to indicate that the prior operation is to be repeated on the next sequential operand.

Abstract: In a procedure for synthesizing circuit designs, a SYNTHESIZE command in a consequence portion of a rule can be used to control the creation of bit-level instances from a description of a more abstract instance whose interface consists of multi-bit signals. The `synthesize` command has a form that identifies multibit signal/part objects in the data base relative to the current multi-bit instance, which are then synthesized over the range of most-significant to least significant bit. A collection of rules, called macrorules are enclosed within a `synthesize` command. An iteration controlled by "current bit", ranging from least significant to most significant bit, ensues. At each step of the iteration, all macrorules are tested and applied if they are `true`. The macrorules can query whether the current bit is a function of the least or most significant bits. The macrorules can also establish connectivity to any signal bit relative to the current, the least significant or the most significant bit.