Abstract: A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses baseband signal samples resulting from analog to digital conversion of a received analog signal followed by digital downconversion. The compressed signal samples are transferred over the serial data link to the baseband processor then decompressed prior to normal signal processing. For the downlink, the baseband processor compresses baseband signal samples and transfers the compressed signal samples to the RF unit. The RF unit decompresses the compressed samples prior to digital upconversion and digital to analog conversion to form an analog signal for transmission over an antenna. Compression and decompression can be incorporated into operations of conventional base stations and distributed antenna systems, including OBSAI or CPRI compliant systems.

Abstract: A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses baseband signal samples resulting from analog to digital conversion of a received analog signal followed by digital downconversion. The compressed signal samples are transferred over the serial data link to the baseband processor then decompressed prior to normal signal processing. For the downlink, the baseband processor compresses baseband signal samples and transfers the compressed signal samples to the RF unit. The RF unit decompresses the compressed samples prior to digital upconversion and digital to analog conversion to form an analog signal for transmission over an antenna. Compression and decompression can be incorporated into operations of conventional base stations and distributed antenna systems, including OBSAI or CPRI compliant systems.

Abstract: An integrated circuit device layout and a method for detecting mask data handling errors are disclosed in which integrated circuit device layout includes a device region in which operable circuitry is disposed. Integrated circuit device layout also includes a verification region in which verification elements are disposed. The verification elements include cells that are duplicates of at least some of the different types of cells in device region and can include structures that are duplicates of at least some of the types of structures in the device region. The patterns in verification region are used in the final verification process to identify mask data handling errors in a mask job deck. Because the patterns in verification region are easy to locate and identify, the time required to perform the final verification process is reduced and the chance of error in the final verification process is reduced.

Abstract: An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a stress reduction layer that extends between the tensile stress layer and the NMOS gate film stack, and a reduced-stress dual stress liner PMOS device having a stress reduction layer that extends between the compressive stress layer and the PMOS gate film stack. In embodiments of the invention additional reduced-stress dual stress liner NMOS devices and reduced-stress PMOS devices are formed by altering the thickness and/or the material properties of the stress reduction layer.

Abstract: An integrated circuit device includes an integrated circuit formed in a semiconductor die and an integrated circuit package containing the semiconductor die. The integrated circuit package includes a thermal interface material substantially between the semiconductor die and a heat spreader of the integrated circuit device for conducting heat from the semiconductor die to the heat spreader. The thermal interface material includes diamond particles and has a thickness selected to reduce capacitance between the semiconductor die and the heat spreader over that of a conventional integrated circuit device without reducing the rate of thermal conduction from the semiconductor die to the heat spreader. As a result, the integrated circuit device has improved electrostatic discharge immunity.

Abstract: A data storage system includes a first circuit board, a plurality of sockets coupled to the first circuit board, an connector coupled to each of the sockets for coupling each of the sockets to external circuitry, and a plurality of memory modules, each memory module disposed within one of the sockets. The memory module includes a circuit board, an integrated circuit device having configurable blocks, DRAM devices that form parallel channels of DRAM memory and flash memory devices that form parallel channels of flash memory. The memory module also includes an interface electrically coupled to the integrated circuit device for coupling input and output between the integrated circuit device and external circuitry.

Abstract: An integrated circuit die is described that includes an array of tiles arranged in columns. The integrated circuit die includes interface tiles having at least one row of through die vias. The integrated circuit die includes metal layers that include horizontal wiring tracks and metal layers that include vertical wiring tracks. At least some of the metal layers having vertical wiring segments include horizontal wiring segments. Each horizontal wiring segment is coupled to a first wiring segment of a horizontal wiring track that is interrupted by the at least one row of through die vias and is coupled to a second wiring segment of the horizontal wiring track that is interrupted by the at least one row of through die vias. Each horizontal wiring segment extends between the at least one row of through die vias and at least one row of through die vias in an adjoining interface tile.

Abstract: An integrated circuit device having configurable resources is configured as a memory controller that includes a plurality of bi-directional pins, an input buffer circuit that is operable to receive SSTL-compliant input and an output buffer that is operable to generate SSTL-compliant output. The input buffer circuit includes a first single-ended buffer coupled to a first voltage source and to a ground voltage. The first single-ended buffer has an input coupled to one of the bi-directional pins and has an output coupled to the control logic of the memory controller.

Abstract: An integrated circuit device includes a stacked die and a base die having probe pads that directly couple to test logic of the base die to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. The base die also includes a first probe pad configured to couple test input, a second probe pad configured to couple test output, and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die to implement the scan chain. The probe pads are coupled directly to the test logic such that configuration of the programmable logic is not required to implement the scan chain.

Abstract: An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a stress reduction layer that extends between the tensile stress layer and the NMOS gate film stack, and a reduced-stress dual stress liner PMOS device having a stress reduction layer that extends between the compressive stress layer and the PMOS gate film stack. In embodiments of the invention additional reduced-stress dual stress liner NMOS devices and reduced-stress PMOS devices are formed by altering the thickness and/or the material properties of the stress reduction layer.

Abstract: A programmable integrated circuit performs an initial partial configuration of the programmable integrated circuit in response to receiving an activation signal. In this way, the programmable integrated circuit enables an initial functionality of the programmable integrated circuit. The programmable integrated circuit then performs a subsequent partial configuration of the programmable integrated circuit for enabling additional functionality of the programmable integrated circuit. In some embodiments, the programmable integrated circuit receives an input signal indicating a stimulus in an environment of the programmable integrated circuit and determines based on the input signal whether to perform the subsequent partial configuration of the programmable integrated circuit or generate a power down signal for powering down the programmable integrated circuit without performing the subsequent partial configuration.

Abstract: An integrated circuit device includes an output buffer having a capacitance circuit configurable in a slew rate configuration or a decoupling configuration. In the slew rate configuration, the capacitance circuit electrically couples a capacitor of the capacitance circuit in a feedback path for reducing a slew rate of a buffered output signal generated by the output buffer. In the decoupling configuration, the capacitance circuit electrically couples the capacitor between a power potential and a ground potential of the output buffer for increasing power noise immunity of the output buffer. The output buffer may have more than capacitance circuit, each of which is individually configurable into the slew rate configuration or the decoupling configuration.

Abstract: An arbiter generates an availability signal indicating whether pseudo-ports are available for receiving data. Each pseudo-port identifies one or more output ports of a packet switch. The availability signal also indicates whether each pseudo-port has a hold. A hold on a pseudo-port indicates that the pseudo-port is being held for an input port of the packet switch. Although the packet switch may complete routing of a data packet in progress to an output port of the pseudo-port that has the hold, the packet switch will not initiate routing of a data packet to an output port of the pseudo-port until each output port of the pseudo-port is available. When all the output ports of the pseudo-port are available, the packet switch can route data of a data packet from the input port for which the pseudo-port is being held to each output port of the pseudo-port.

Abstract: A method for forming a stacked-die structure is disclosed in which a buried oxide layer is formed in a semiconductor wafer. Device layers and metal layers are formed on the face side of the semiconductor wafer, defining dice, with each die including an interconnect region. Openings are etched in the interconnect regions that extend through the semiconductor wafer so as to expose portions of the buried oxide layer. Conductive material is deposited within the openings so as to form through-die vias. The semiconductor wafer is then attached to a wafer support structure and material is removed from the backside of the semiconductor wafer so as to form an oxide layer having a thickness that is less than the initial thickness of the buried oxide layer.

Abstract: A method and apparatus for generating a random bit stream in true random number generator fashion are described. Two periodic signals are employed in generating the random bit stream. A first periodic signal having preferably an approximately fifty percent duty cycle and jitter induced by supply and substrate noise is sampled by a second periodic signal that is relatively jitter-free and of a lower frequency than the first periodic signal.

Abstract: A die seal structure for sealing integrated circuit devices formed on a semiconductor substrate. The die seal structure includes a die seal and a junction diode. The die seal only connects to the semiconductor substrate through the junction diode, thereby reducing noise coupling through the die seal. In another aspect of the present invention the die seal structure includes a die seal and a bipolar structure. In this embodiment the die seal only connects to the semiconductor substrate through the bipolar structure.

Abstract: Sidewall spacers are disclosed that extend on opposing sidewalls of gate stacks. The sidewall spacers have improved profiles to suppress or eliminate void formation between the gate stacks during gap-filling A gate dielectric layer is formed on a semiconductor substrate. Then, a gate stack 24 having a sidewall is formed over the gate dielectric layer. The gate stack 24 comprises a conductive layer 28 and a hard mask 30 overlying the conductive layer 28. A liner 32 is selectively deposited over the gate stack 24 such that the liner 32 is deposited on the hard mask 30 at a rate lower than the rate of deposition on the conductive layer 28. Thus, the liner 32 is substantially thinner on the hard mask 30 than on the conductive layer 28. A nitride spacer is formed over 34 the liner 32. A PMD layer is formed over the resultant structure, filling the gaps between adjacent gate stacks.

Abstract: A buffer bypass circuit for reducing latency in information transfers to a bus is described. Access to the bus is governed by a bus arbiter employing a bus parking scheme. The buffer bypass circuit comprises a multiplexer and logic configured such that the information to be transferred is either buffered in a buffer if a grant generated by the bus arbiter indicates that the bus is unavailable, or transferred directly to the bus if the grant indicates that the bus is available and the buffer is empty at the time.

Abstract: A method for forming a photoresist structure that does not have swelling defects. A layer of low activation energy deep ultraviolet photoresist is disposed over a layer that is to be patterned. A layer of high activation energy deep ultraviolet photoresist is then deposited such that the layer of high activation energy photoresist directly overlies the layer of low activation energy photoresist. The two photoresist layers are then processed by performing exposure, post-exposure bake, and development steps to form a photoresist structure. An etch step is then performed so as to form a patterned layer that does not have swelling defects.

Abstract: An apparatus and a method for reducing layer separation and cracking in semiconductor devices. A structure is formed over a semiconductor wafer that includes die separated by scribe streets and that includes probe pads for testing die. A notch is cut within a scribe street so as to expose an open area that does not contain any probe pad and that does not contain any metal layers. The wafer is then severed into semiconductor devices by extending a cutting blade through the open area. A semiconductor device is then electrically and physically coupled to a ball grid array substrate to form a ball grid array device having reduced layer separation and cracking.