Abstract: A data link processor (peripheral-controller), for managing data transfers to/from multiple disk drive modules, provides a hardware self-test operation to its subsystem card units when it is powered on. The data link processor momentarily disables its interfaces to the peripheral disk drives and the host computer to execute test operations and to indicate either the integrity condition or fault condition of its card units. Each card unit also has a pushbutton for self-test initiation and a local light-emitting diode which lights up and stays lit up if the card unit is misfunctioning to indicate a failed card unit. Further, the connected host computer can initiate the self-test operation for the peripheral-controller for integrity testing.

Abstract: A synchronizer is comprised of a voltage amplifier having an input terminal for receiving a voltage sample and an output terminal for generating an output voltage that is inversely proportional to the voltage of the input terminal. Also, a first feedback circuit couples the output terminal to a control transistor internal to the amplifier, and a second feedback circuit couples the output terminal to the input terminal. The first feedback circuit together with the control transistor has a fast response time, in comparison to the second feedback circuit; and it operates to quickly increase the output voltage when the voltage sample on the input terminal is below a predetermined level, and vice versa, without altering the voltage sample on the input terminal. And, the second feedback circuit operates to slowly modify the voltage sample on the input terminal in inverse proportion to the output terminal voltage.

Abstract: A multiplier circuit is comprised of multiple arrays of logic cells. Each array has input lines for receiving two multibit binary numbers that are to be multiplied together; and each logic cell includes an AND gate for producing single power product terms by multiplying together one bit from each of the two numbers. These cells are arranged in the arrays such that the total quantity of single power product terms of any particular power in the respective arrays is within 30% of each other. One subset of cells of each array also includes a respective two-bit adder, and another subset of cells of each array includes a respective three-bit adder. These two-bit and three-bit adders are interconnected within each array to form an intermediate result, in parallel with the other arrays, which consists of a partial sum of all product terms in the array together with no more than one remaining carry-in for each bit of that partial sum.

Abstract: An electrostatic discharge protection circuit includes a P.sup.- doped channel and an N.sup.- doped channel that form a serial path between a signal pad and a transistor. Holes are depleted from the P.sup.- doped channel in response to a negative electrostatic discharge on the input signal pad; and electrons are depleted from the N.sup.- doped channel in response to a positive electrostatic discharge on the input signal pad. When either depletion occurs, the path from the signal pad to its transistor is open circuited; and so the transistor is protected. Conversely, when no electrostatic charge exists on the signal pad, the path through the P.sup.- doped channel and the N.sup.- doped channel is highly conductive; and so signals pass between the pad and the transistor very quickly.

Abstract: A tester-verifier apparatus operates to select a single one of a plurality of system clocks to verify that the clock width falls between accepted parameters. Secondarily, the apparatus selects representative clock signals for comparison with a reference clock to verify that the skew falls within accepted parameters. Additionally the apparatus can measure the exact time value of any pulse width or skew relationship to within 500 picoseconds (10.sup.-12). Any selected system clock signal is split into two channels, one of which has a controlled delay time programmed by a microprocessor to develop minimum and maximum pulse parameters against which the selected clock signal is logically compared to see if the parameters are satisfied.

Abstract: A method of fabricating a tapered via hole in a polyimide layer of an integrated circuit includes the steps of: disposing a layer of SiO.sub.2 on the polyimide layer and a layer of photoresist on the SiO.sub.2 such that the layers have an opening which exposes a region of the polyimide layer for the via hole; etching the exposed polyimide region partway through the polyimide layer, while simultaneously etching back the photoresist on the sidewalls of the opening to thereby uncover a strip of SiO.sub.2 adjacent to the perimeter of the exposed polyimide region; enlarging the exposed region of the polyimide by etching the uncovered strip of SiO.sub.2 ; and repeating the etching step and enlarging step a predetermined number of times.

Abstract: This invention is an improvement to an integrated circuit package which is of a type that includes a package body with multiple chip attach regions for holding respective integrated circuit chips, signal pads around the chip attach regions, an array of I/O pins on the package body, a first set of conductors in the package body which selectively connect some of the signal pads to the I/O pins, and a second set of conductors which selectively connect some of the signal pads to each other but not to any I/O pins.

Abstract: An easily installable and easily expandable electromechanical memory assembly for a data processing system includes: a frame having a backplane, a plurality of printed circuit board connectors on the backplane, and conductors on the backplane which interconnect the connectors; a controller on a printed circuit board which is plugged into one of the connectors and consists essentially of logic circuitry for generating and receiving control signals on the backplane conductors; and multiple data storage units; each unit being mounted on a separate printed circuit board, plugged into a separate connector, and consisting essentially of a mechanical drive mechanism which reads data by physically moving a data storage medium past a data sensor in direct response to the control signals from the controller on the backplane conductors.

Abstract: A liquid cooled electronic circuit includes a printed circuit board having two oppositely facing surfaces, electronic components mounted on one of the two surfaces, and conduits which carry a liquid and touch the electronic components to cool them; wherein a frame is also provided for holding the conduits snugly against the components without overstressing the printed circuit board. This frame is characterized as having: (a) a first set of contacts which engage the conduits; (b) a second set of contacts which engage the surface of the printed circuit board opposite the one surface; (c) the contacts of the second set being spaced apart and located at predetermined distances from the board's perimeter; and (d) fasteners for urging the conduits against the electronic components by moving the first and second sets of contacts toward each other with the conduits, the electronic components, and the printed circuit board lying therebetween.

Abstract: A wide ROM-PROM memory is structured of multiple memory chips in parallel plus an auxiliary parity memory chip to hold parity bits for each corresponding addressable location in each memory chip. Sensing means is provided to check parity of data bits read from each memory location to verify integrity of the read-out.

Abstract: A parity detection scheme for a wide memory structure of RAM memory chips provides an auxiliary RAM parity memory chip to store parity data for each corresponding input line of each memory chip corresponding for each address of each memory chip. This parity data is compared to comparable parity data which is read-out of any corresponding address of each of said memory chips.

Abstract: A multichip integrated circuit package comprises a thin planar body which has top and bottom major surfaces. Conductors, for carrying electrical signals, are integrated into the body and include input/output terminals on one portion of the bottom surface. Downward-facing cavities for holding respective high power integrated circuit chips extend from another portion of the bottom surface into the body, and upward-facing cavities for holding respective low power integrated circuits extend from the top surface into the body. Small thermal resistance for the high power chips is achieved, and footprint is simultaneously minimized by locating the upward-facing cavities over the terminals.

Abstract: A display device adapted to display one or more characters side by side in a row and including an insulating support plate, on the top surface of which are formed a plurality of groups of conductive members, each group being adapted to be energized to display a character. The device includes various configurations of anode electrodes, shielding electrodes, and interconnections of common characters in each group to provide manufacturing economies.

Abstract: A display panel comprising a plurality of gas-filled cells, each having a pair of energizing electrodes and adapted to be energized in groups to display characters. The panel also includes a plurality of cells which are adapted to be energized so that they glow continuously and facilitate the turning on of the groups of cells which are used to display a character. These auxiliary energizing cells are hidden from view so that they perform their function without being seen and without interfering with viewing of the primary characters.

Abstract: The bracket includes an elongated base member having a series of first apertures for receiving (1) metallic connectors for making electrical contact with the electrodes of a display panel, and for receiving (2) a pair of alignment members for properly aligning the panel when it is coupled to the bracket. The elongated base member also includes an array of second apertures which are adapted to receive a plurality of vertical support members which are constructed so that they can be secured to a printed circuit board or the like. The vertical members can also be provided with movable arms for engaging and holding the display panel. The base member and the upright members are designed so that two base members can be connected together in series, and they can be held together mechanically by an upright member which engages both base members simultaneously.