Abstract: An avalanche photodetector (APD) is made from composite semiconductor materials. The absorption region of the APD is formed in a n-type InGaAs layer. The multiplication region of the APD is formed in a p-type silicon layer. The two layers are bonded together. The p-type silicon layer may be supported on an n+ type silicon substrate. A p-n junction formed at the interface between the silicon layer and the substrate. Alternatively, the n-type InGaAs layer may be supported on an InP substrate. In this case, a p-n junction is formed by making n-doped surface regions in the p-type silicon superlayer. In either case, the p-n junction is reverse biased for avalanche multiplication of charge carriers. The maximum of the electric field distribution in the APD under reverse bias operating conditions is located at p-n junction. This maximum is at a distance equal to about the thickness of the p-type silicon layer away from the absorption region.

Abstract: A programmable and adaptive electronic filter for filtering digital signals. The filter uses a table which contains the outputs corresponding to all possible inputs, so that the filter may be constructed of memory, adders and multiplexers, and does not require multipliers. The input sample is used as an address to determine the location in the memory which contains the output corresponding to that input. The table of outputs is placed in a particular order such that the change between the inputs corresponding to each two adjacent locations is a single digit, thus allowing the table to be easily calculated, since the difference between the outputs in those two locations is two times the weighting coefficient for the digit in the input which is changed. Adaptive filtering is accomplished by using a second filter which has as its input the difference between the actual output of the filter and the desired output, and as its output changes to the weighting coefficients of the filter.

Abstract: A self-supporting convex cover for spacecraft hardware is described. In the preferred embodiment, the cover is made of a laminated material. Strips of material are inserted into the laminate in a channel shape, such that sufficiently rigid box beam structures are formed in a pattern to hold the convex shape. Ribs of foam may be placed between a layer of the laminate and the strips of material to provide the channel shape. The cover is attached to the spacecraft hardware by one or more drawstrings which are laced through the perimeter of the cover. With appropriate materials, the resulting assembly is light, inexpensive, easy to assemble, and transparent to radio frequencies, yet sturdy enough to maintain its shape during launch.

Abstract: A method and apparatus for playing a first sequence of sounds represented by data stored in memory synchronously with a second sequence of sounds represented by data stored in memory, at any point during the playing of the second sequence of sounds. A point in time is selected at which a specific sound in the first sequence of sounds must be played at the same time as the specific sound in the second sequence of sounds for the two sequences to be synchronous. The number of sounds in the second sequence which have been played before the current sound being played is counted and used to determine which sound in the first sequence is synchronous with the current sound in the second sequence. The data representing both sounds is then retrieved and used to generate, i.e. to "play," the identified sound in the first sequence simultaneously with the current sound of the second sequence.

Abstract: A non-contact tonometer is described for measuring the intra-ocular pressure (IOP) of the eye. An ultrasonic power transducer directs an ultrasonic beam onto the eye and the force generated by the radiation pressure causes indentation or applanation which is detected by ultrasonic or optical means. An optical system provides an image of the eye with appropriate alignment beams injected through a beam splitter for positioning the device with respect to the eye. An additional ultrasonic beam may be used to measure the range to the eye. Another optical means is utilized to measure applanation or indentation; alternatively, an additional ultrasonic transducer and beam could be used. Operation of the device may be through continuous wave or pulsed excitation of the ultrasound. Feed-back control of the ultrasound power level is possible using an additional ultrasonic transducer for measuring the power levels to augment measurement accuracy.

Abstract: A system and a method are described for optimizing the sequencing and time requirements for compiling large sets of source code residing in multiple hierarchical file directories using an abstracted logical description of the hierarchical file relations existing between directories. The system consists of a logic processor working in concert with input and output file registers, a match register, and an abstracted tree register for the purpose of creating a identifying, comparing, and sequencing file names in a final description of the global directory. The method iteratively identifies the primary input files and the intermediate input files for a given output file for each of a series of directories, inverts the casual relationship between the output file and its intermediary input files, and accumulates and stores these relationships in a sequential manner for subsequent use.

Abstract: A method and apparatus for storing and retrieving multi-dimensional data in which a multi-level data structure is defined wherein one level contains those dimensions chosen by the user to result in dense data and the other level contains the remaining sparse data combinations. The dense dimensions specified in any given case are used to determine the basic block size used to store information. The remaining sparse dimensions are used to create the upper level structure which is used to point to the block which contains the desired information. Depending upon the sparseness of the data, different types of upper level structure may be used. Both the variable data block size and the choice of pointer structure may be used to balance the memory required against the speed of retrieval.

Abstract: A system and method are described for decreasing the synthesis time required for realizing digital circuit net lists using library logic elements. The system consists of a logic processor working in concert with a cell library register, a hierarchical cell array memory, and a match register, for the purpose of hierarchically ordering, matching and eliminating equivalencies in the canonical forms of library cells. The method includes the reduction of all library elements to their canonical forms and the hierarchical ordering of the these canonicals based on the number of nodes contained in each element. Once ordered, the canonicals are mapped by logic elements having fewer nodes, beginning with the simplest of the canonical forms. Redundantly mapped logical elements are eliminated and the resulting reduced set is stored for subsequent use.

Abstract: An apparatus and method for improving the printing and edge enhancement of laser printers comprises a video clock counter, an input selector, a calibration selector, a mode selector, a decoding array, a register, memory and an address counter. The gray and edge enhancement circuit modifies the data received from the laser print controller to smooth edges in the image sent to the laser. The present invention compares each pixel and surrounding pixels in an area seven pixels wide and seven pixels long to correction bit patterns. If a match is found the pixels are modified to enhance any edges defined by the pixels. The gray and edge enhancement circuit also includes an operating mode in which shades of gray may be printed with a resolution of 150 dpi. The circuit uses the decoding array to pulse width modify the input data to various shades of gray.

Abstract: A Quasi Radix-16 Butterfly comprises an radix-4 butterfly processor and on-board memory with external memory addressing changes from a conventional radix-4 butterfly processor. On-chip cache memory is included to store data outputs of the radix-4 butterfly processor for application as data inputs to the radix-4 butterfly processor in a second series of butterfly operations to implement high-speed processing that is maximally execution-bound.

Abstract: An improved circuit layout-verifying system and method operates on a plurality of polygons that are representative of an electrical node to test the proper or improper connection of each polygon to another contiguous polygon and designates for display those polygons that represent improper connections between known or identified reference points on the node. Traversals along a sequence of contiguous polygons between known reference points on the same electrical node are designated as proper connections or successes, and traversals along a sequence of contiguous polygon between reference points associated with different electrical nodes are designated as improper connections or failures at least along a portion of the sequence. Data from all traversals of all polygons from all known reference points is then analyzed to remove unambiguous sequences of polygons for the improperly connected electrical nodes.

Abstract: A computer system and computer-implemented method for compacting the geometrical area of a hierarchical integrated circuit layout. The present invention is particularly adapted for use with layouts including over-the-cell routing (OTCR). The inventive method includes the general steps of normalizing the cells, compacting the cells, then reconstructing the layout that includes the normalized cells. More particularly, the step of normalizing the cells includes initial step of identifying an overlapping object produced from the OTCR that overlaps one of the instances. That overlapping object is then divided into an overlapping segment and a non-overlapping segment. The overlapping segment is then removed from the cell and copied into the leaf cell of the overlapped instance. The overlapping segment is defined as a special object of the cell into which it is copied.

Abstract: A method for synchronously writing data from memory to a disk drive memory device minimizes the number of actual I/O operations by writing data to disk in large chunks. The method comprises the steps of: allocating an array for saving buffer pointers; mapping the data to the disk space; allocating a buffer for each block of disk space; copying the data into the buffer; saving a pointer to the buffer in the array and then writing physically adjacent blocks to disk in one I/O operation. The method also updates and reads address blocks in the buffer pool and writes them to disk only at the end of the write request.

Abstract: An EEPROM stores multiple sets of video display parameters for a multi-frequency video display. A microcontroller receives input from a user, changes the stored display parameters and outputs changes in the parameters to the video display. The microcontroller also controls video display apparatus that displays on-screen menus and value indicator graphs for facilitating user input. The video display apparatus incorporates a video clock synchronized to the horizontal synchronization signal of the multi-frequency display, to keep the displayed menus synchronized regardless of the current frequency. In addition, the video display apparatus elongates displayed characters at higher frequencies to control the absolute size of displayed characters across frequencies. The present invention provides for changes to video display parameters, and for resetting the display parameters to factory standards, without manipulating electromechanical devices such as potentiometers.

Abstract: A control circuit for a switching power supply. First and second transformers for outputting different voltages are controlled by first and second switches. The switches are controlled by first and second control means which are turned on when the applied voltage exceeds a specified start-up voltage, and off when the voltage drops below a lower shut-down voltage. A reference voltage charges a capacitor, which is then added to the operating voltage of the circuit so that the start-up voltage can be applied even though the operating voltage of the circuit is lower than the start-up voltage. A third control means controls the change from one switch to the other at the desired voltage levels. The use of lower operating voltages allows the circuit to more rapidly drop below the shut-down voltage when abnormal operation occurs.

Abstract: A collapsible, dish shaped assembly, for example, for use with a satellite. The dish shaped surface is assembled from two sets of rigid panels. The first set of panels is rotated into position on hinges, which attach the panels to a base. The second set of panels is then rotated into position, also on hinges at the base, such that the second set of panels fill in the spaces between the panels of the first set. A latch connects each pair of adjoining panels. The latch comprises a protrusion which slides into a corresponding cavity. The resulting latch is resistant to lateral force. The latching process is facilitated by magnetic forces, which also add to the final latching force. The latches can be disengaged by jacking screws.

Abstract: A ground bouncing reducing circuit comprises a first control means, a second control means and an output means for generating an output signal at a fourth output terminal. The first control means generates a first control signal at a first output terminal and a second control signal at a second output terminal in response to an input signal. The first control signal and the second control signal are not asserted at the same time. The second control means generates a third control signal at a third output terminal in response to the first control signal and the second control signal. The ground bouncing phenomenon is reduced when the output signal changes state.

Abstract: A memory system capable of incorporating defective memory chips is provided. The system includes a first memory chip having a first data signal line and being logically divided into an upper half and a lower half, a controlling circuit responsive to a first indicative address signal and an address strobe signal for outputting therefrom a second indicative address signal and a first and a second output enabling signals, and a second memory chip being logically divided into an upper and a lower halves and having a second data signal line electrically connected to the first data signal line so that only one of the first and second chips is accessible at any time.

Abstract: A constant output circuit wherein outputs are not a function of deviations of reference voltage. More specifically, the outputs maintain their logic "1" and logic "0" values, even when there are reference voltage noise or fluctuation in the circuit. This constant output circuit having a logic "1" output node and a logic "0" output node comprises a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor. A logical inversion operation is performed between a first input node and a first output node of a logic circuit. The first input node is coupled to the logic "1" output node. The gate of said first PMOS transistor is coupled to the first output node of the logic circuit, the source to the power supply, and the drain to said logic "1" output node. The gate of said second PMOS transistor is coupled to the logic "1" output node, the source to the power supply, and the drain to said logic "1" output node.