Abstract: Briefly, in accordance with one embodiment of the invention, a technique and device are described that may allow a user to determine if the engine in a classic or antique automobile is original. The common characteristics of the factory applied markings of known original engines may be identified. All or a portion of an unknown engine may then be compared to those common characteristics to determine if the unknown engine was likely stamped using the same stamping tool as the known original engines.

Abstract: Briefly, in accordance with one embodiment of the invention, a system includes two boards coupled by a bus. The bus having a dual-terminated transmission line that communicatively couples a memory control hub with a memory repeater hub that each have a Rambus ASIC Cell (RAC). Briefly, in accordance with another embodiment of the invention, a connector has two metal traces that are of different lengths. The parasitic capacitance of the longer metal trace is increased so that the impedance of the two metal traces is substantially equal.

Abstract: Briefly, in accordance one embodiment of the invention, a method of suspending a network connection used for low priority transmissions between a client platform and a server platform includes: determining a characteristic of a transmission between the client platform and the server platform, said characteristic consisting essentially of a high priority transmission and a low priority transmission; and suspending the connection if the characteristic of the transmission comprises a high priority transmission briefly, in accordance with another embodiment, a method of using a network connection between a client platform and a server platform includes: producing on one of the platforms a list of Uniform Resource Locators (URLs) from a requested network page, said list comprising links in said requested network page; and pre-fetching via said connection at least one of said URLs to said remote proxy server.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.

Abstract: Briefly, in accordance with one embodiment of the invention, a flip-flop operates as a master-slave flip flop in a test mode and operates as a pulsed latch in normal operation. Two clock signals having non-overlapping transitions are used to provide and control the flow of input data.

Abstract: An electrostatic discharge circuit may include an RC timer that may be used to control the operation of two or more tiers within the ESD circuit.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has two voltage domain regions. The integrated circuit provides for changing the operational voltage of one of the voltage domain regions with respect to the other.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage generator that selectively increases the voltage potential on the channel region of a transistor relative to the source region of the transistor. The voltage potential may be provided to a diffusion region in the well regions with transistors.

Abstract: Briefly, in accordance with one embodiment of the invention, a processor has a loop buffer and a cache that provides requested information to a processor core.

Abstract: A system or method to partition data in a memory based at least in part to a data type, and to refresh the memory based at least in part to the data type. The claimed subject matter relates to organizing data in a memory for a refresh operation.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.

Abstract: The invention relates to a phase-change memory device. The device includes a lower electrode disposed in a recess of a first dielectric. The lower electrode comprises a first side and a second side. The first side communicates to a volume of phase-change memory material. The second side has a length that is less than the first side. Additionally, a second dielectric may overlie the lower electrode. The second dielectric has a shape that is substantially similar to the lower electrode. The present invention also relates to a method of making a phase-change memory device. The method includes providing a lower electrode material in a recess. The method also includes removing at least a portion of the second side.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a sense amp connected to a plurality of bit lines with bit line transistors. Each of the bit line transistors may be connected to a sense amp enable transistor so that together, the coupling and sense amp enable transistors connect the sense amp to a power supply voltage.

Abstract: Briefly, in accordance with one embodiment of the invention, an apparatus includes an integrated circuit that has the capability to schedule transferring processes that have an individual identification number. At least a portion of each individual identification number is used to indicate the presence of each of the transfer processes. Briefly, in accordance with another embodiment of the invention, an integrated circuit having a scheduler of transfer processes, each of the transfer processes having an identification number. The scheduler is coupled to a memory array of bits, and a portion of each identification number is used as a portion of an address to the memory array of bits. Briefly, in accordance with yet another embodiment of the invention, a method of scheduling requests for the transfer of data where each request having an identification number. The identification number is used in addressing a bit in an array of bits and set to indicate the request for the transfer of data.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit comprises a first stage that provides differential outputs in one mode and substantially equal outputs in another mode.

Abstract: Briefly, in accordance with one embodiment of the invention, a node includes: a circuit. The circuit is configurable based, at least in part, on control signals external to the node to be applied to the node via a power distribution system formed when the node is coupled to a plurality of nodes. The circuit includes the capability to deliver and to interrupt the delivery of power via the power distribution system.

Abstract: Briefly, in accordance with one embodiment of the invention, a DC-to-DC converter includes: a synchronous rectifier converter. The synchronous rectifier converter includes a buck converter. The transformer of the synchronous rectifier converter employs less than five windings on the secondary.

Abstract: Briefly, in accordance with one embodiment of the invention, a digital-to-analog cell includes an analog circuit that provides, at least in part, an output signal. Transistors may be coupled to the analog circuit to provide source-side switching of the analog circuit.

Abstract: One embodiment of the present invention is a method for providing security for a transmission of information in an ADSL environment using a DMT modulation technique. The order of the frequency orthogonal subchannels used in the DMT technique is scrambled according to a permutation cipher. The key for this scrambling operation is scrambled with the subscriber's public key, and is encoded according to a CDMA technique for transmission through the ADSL channel approximately concurrently with the information. The encoded key and the DMT data subblocks are recovered from the secured transmission. The encoded key is decoded according to the CDMA technique to generate the decoded key. The decoded key is used to assign an order to the subblocks of data.

Abstract: Binary and Quadrature Feher's (F)-Modulation/Transmitter-Receiver (Transceiver) with reduced envelope fluctuations and peak radiation, increased efficiency delivered by baseband, intermediate frequency (IF) connected RF (radio frequency), Infrared (IR) and other devices. A subclass of these systems has a constant envelope. Power advantages, robust BER performance and linearly or nonlinearly amplified narrow spectrum without the pitfalls of conventional BPSK, DBPSK QPSK and pi/4 QPSK is attained. Feher's FBPSK improved efficiency transmitter is compatible with conventional BPSK receivers. FBPSK modems are based on using quadrature structure where Q channel data is inserted in quadrature with I channel data for certain applications. The Q channel data is “offset” from the changed data by an amount selectable between zero (0) and a specified time. Further improvement in the spectrum is attained using correlation between I and Q channels. FBPSK modem is shown to meet the IEEE 802.