Abstract: A television picture magnification system which provides real-time magnified video images includes a memory system which stores L horizontal line intervals of samples representing one field of the unmagnified video image during a first time interval and which provide K of those L lines of samples during a second time interval offset from the first time interval by less than one field period. The K lines of samples provided by the memory are interpolated by the system to develop L lines of samples which represent one field of the magnified image. The offset delay between the first and second time intervals ensures that any field of the magnified image includes samples from only one field of the unmagnified image.

Abstract: A television receiver includes a phase-locked loop (PLL) which generates a clock signal having a frequency of N times the line frequency and being phase-locked to the horizontal line synchronizing signal. The clock signal produced by this PLL has a frequency which tends to jitter between N+1 and N-1 times the line frequency. To compensate for this jittering in the frequency of the clock signal, phase alignment circuitry is coupled to the PLL to align the phase of the clock signal to the horizontal drive signal produced by the PLL on the occurrence of each horizontal drive pulse. The PLL also includes a delay element which delays the horizontal drive signal applied to the phase comparator of the PLL. This delay element effectively advances the phase of the horizontal drive signal and the line-locked clock signal with respect to the horizontal sync signal to compensate for signal processing delays imparted in the generation of the horizontal drive signal and the clock signal.

Abstract: A dual port video memory system includes a serial-to-parallel converter coupled to the input data port and a parallel-to-serial converter coupled to the output data port. Four-bit pixel values are clocked into the serial-to-parallel converter synchronous with an input clock signal and are provided by the parallel-to-serial converter synchronous with an output clock signal. The input and output clock signals may have different frequencies, but the negative-going edges of each of these clock signals are synchronized to the negative-going edges of a master clock signal.

Abstract: A full motion color digital video signal is compressed, formatted for transmission, recorded on compact disc media and decoded at conventional video frame rates. During compression, regions of a frame are individually analyzed to select optimum fill coding methods specific to each region. Region decoding time estimates are made to optimize compression thresholds. Region descriptive codes conveying the size and locations of the regions are grouped together in a first segment of a data stream. Region fill codes conveying pixel amplitude indications for the regions are grouped together according to fill code type and placed in other segments of the data stream. The data stream segments are individually variable length coded according to their respective statistical distributions and formatted to form data frames.

Abstract: A video features processor for use with a display device includes a first clock that is line locked to the display and a skew-shifted second clock that is phase locked to the horizontal sync component of an auxiliary video signal. An A/D converter, responsive to the skew-shifted clock, develops digital samples representative of the auxiliary video signal. A clock transfer circuit, responsive to the line-locked and skew-shifted clocks, translates digital samples occurring synchronously with the skew-shifted clock signal to digital samples occurring synchronously with the line-locked clock signal. The digital samples occurring synchronously with the line-locked clock signal are stored in a memory.

Abstract: A digital video zoom system includes circuitry for writing image samples into a memory at a standard rate and for reading samples from the memory at a reduced rate. Samples are read from the memory under control of a digital accumulator which repeatedly adds a value N to a stored value, modulo M, to obtain a new stored value. Samples are read from the memory only when an overflow condition is detected in the accumulator. The four most significant bits of the value held by the accumulator are also used to develop interpolation factors which are used to combine successive sample values provided by the memory to develop interpolated sample values which are used to produce the enlarged image. The image is increased in size by a factor of M/N relative to an unmagnified image.

Abstract: A divider divides down the output of a high frequency oscillator to generate a master clock signal MCS for the purposes of sampling an incoming composite video signal CVS. A skew measuring circuit latches the current state of the divider at a predetermined edge of every incoming horizontal sync signal pulse IHSSP to provide skew data representative of the timing or phase offset between the clock signal MCS and the incoming horizontal sync signal IHSS at the start of each new line of picture information.

Abstract: A burst locked phase locked loop (PLL) includes a relatively wide-band voltage controlled oscillator. This PLL may erroneously lock at a frequency which differs form the frequency of burst by an amount equal to the horizontal line frequency. To prevent this side-locking condition, the PLL includes circuitry which changes the frequency of the signal produced by the VCO when the number of cycles of the signal provided by the PLL during one horizontal line interval corresponds to the number which would be obtained in a side-lock condition.

Abstract: A television pix-in-pix system includes a pixel memory for storing one field of pixel intensity values of a television signal. A 1-bit overlay indication signal representative of pixel address locations defining a desired indicia on the TV screen is stored in an associated bit map memory. A digital multiplexor having input terminals coupled for respectively receiving the pixel intensity values and suitable overlay display values, and responsive to the overlay indication signal, provides the overlay display values when the overlay indication signal is a logical one, and provides the pixel intensity values otherwise, thereby generating the desired indicia as a part of the inset image on the TV screen.

Abstract: An interpolating apparatus for generating a pair of non-identical, interlaced fields from a single stored field of video signal. One of the interlaced fields is generated by adding three-fourths of one line's amplitude to one-fourth of the next line's amplitude. The other interlaced field is generated by adding one-fourth of said one line's amplitude to three-fourths of the next line's amplitude.

Abstract: A picture-within-a-picture television receiver includes circuitry for displaying a reduced-size frozen image developed from an auxiliary signal as an inset in the main image. To develop signals representing two fields of the compressed auxiliary image, the system includes circuitry which processes first and second groups of successive horizontal line intervals of one field of the auxiliary video signal to develop signals representing mutually corresponding horizontal line intervals in two successive fields of the compressed auxiliary video signal.

Abstract: A picture-in-picture television receiver for which the viewer may change the size of the inset image includes an adaptive anti-aliasing filter. Composite video signals which produce the inset image are applied to a separation filter which attenuates the chrominance components to provide separated luminance signals. The luminance signals are applied to a second filter which includes a variable delay element and an adder. The luminance signals are applied to one input port of the adder and to the delay element. The signals provided by the delay element are applied to the second input port of the adder. The delay element provides time delays which may be expressed by the equation T=K.sub.2 .tau.+PK.sub.1 .tau. where .tau. is a fixed amount of time, K.sub.1 and K.sub.2 are constants and P is a variable. The frequency response characteristic of the filter is changed by changing the value of P.

Abstract: A pix-in-pix television signal processing system develops a composite video pix-in-pix signal representing a reduced-size auxiliary image insert in a full-sized main image. The auxiliary video signal is separated into luminance and chrominance components by filtering circuitry. The luminance signal is subsampled in a ratio of one to four and the chrominance signal, which is composed of two color difference signals modulating quadrature phase related subcarrier signals, is applied to circuitry which interpolates between selected pairs of samples to develop a frequency converted chrominance signal, representing the two quadrature phase related color difference signals modulating quadrature phase related subcarrier signals having frequencies that are one-quarter the frequency of the original subcarrier signal. The frequency converted chrominance signal and subsampled luminance signal are combined to generate a composite video signal representing the reduced-size auxiliary image.

Abstract: Circuitry for forming the twos complement or ones complement of M-bit binary numbers is described. The circuitry includes M stages each of which contains an exclusive NOR gate. A first input terminal of the exclusive NOR gate is coupled to receive one bit of the input value and a second input terminal is coupled to receive the carry output signal from the previous stage. A logic one or logic zero is applied to the second input terminal of the stage which processes the least significant bit of the binary word if the circuitry is to provide a twos complement or ones complement value respectively. The carry output signal for each stage is generated by ANDing a logically inverted version of the input bit signal with the carry input signal applied to the stage. An application of the complementing circuitry in an absolute value circuit is also described.

Abstract: An adaptive television deghosting system operates on modulated video signals including a direct signal component and one or more ghost signal components. The system uses synchronously demodulated in-phase and quadrature-phase baseband video signals as the respective real and imaginary input signals to a complex IIR filter. The filter coefficients are developed adaptively from preset initial values using the signals provided by the filter during a training interval. The training interval includes the interval between the leading edge of the vertical sync pulse and the first serration pulse of each field. The filtered training signals are subtracted from a sync-tip reference value to develop a signal which is proportional to the error in the filter coefficient values. The error signal values corresponding to ghost signals are multiplied by the complex conjugate of the training signal values which represent the analogous sampling points of the direct signal.

Abstract: A digital television receiver which uses a line-locked clock signal employs chrominance signal demodulation circuitry which produces a digital oscillatory signal that is locked in phase to the color reference burst signal component of the incoming video signals. An analog voltage controlled oscillator generates an oscillatory signal having a frequency of approximately twice the color subcarrier frequency. This signal is combined with the composite video signals and the combined signal is digitized by an analog to digital converter. The digitized oscillatory signal is separated from the combined digital signal and is used to synchronize a digital phase locked loop. The digital phase locked loop generates two quadrature phase related signals having frequencies that are one-half the frequency of the analog oscillatory signal. These two signals are used to synchronously demodulate the chrominance signal components of the incoming video signals to obtain two quadrature phase related color difference signals.