Abstract: Design methodologies and techniques for significantly increasing logic density by stitching multiple reticles together are disclosed. The invention teaches various techniques to ensure continuity of interconnections and sealing mechanisms across the stitch region. The stitch extended device is readily scalable to allow quick transitions to next generation technologies.

Abstract: An indirect current sensing circuit and method for current limiting output driver circuitry is disclosed. The present invention is capable of preventing device damage and circuit disruption by maintaining output voltage signal integrity and consuming negligible power. Furthermore, the indirect current sensing circuit and method is independent of semiconductor process variations and thus is more reliable over prior art current sensing techniques. The indirect current sensing circuit and its method of current limiting, according to the present invention, can reliably drive transmission lines in networking system and communication applications.

Abstract: An asynchronous sample rate tracker based on a phase-locked loop quickly locks to an input sample rate, even when the input sample rate equals the resident, or internal, sample rate of an asynchronous digital sample rate converter. The phase difference between the input write data and output read data is maximized to reduce data lost due to excursions in the input sample rate. In one embodiment, a binary shift register is used to generate a read pointer step size according to the derivative of the difference between a write pointer position and a read pointer position.

Abstract: A voltage regulated charge pump is disclosed which is capable of regulating its output voltage without radiating switching noise or consuming more power than is necessary to maintain the output at its targeted level. The voltage regulated charge pump circuit and its method of regulation, according to the present invention, can reliably drive transmission lines in networking system and communication applications.

Abstract: A circuit for implementing digital delay lines that includes a main memory, a cache memory, and a processor. The main memory implements at least one digital delay line, as many delay lines as required by a digital signal processing (DSP) program running on the processor, up to a predetermined number. The delay lines contain data samples to be operated on, or produced by DSP program. The cache memory implements a number of delay caches that temporarily store data samples and support the delay lines. Each delay line is associated with a read cache and a write cache. A block of data samples are “pre-fetched” from a delay line in the main memory and provided to the associated read cache. The data samples in the read cache are then accessed, as needed, by the processor. Data samples generated by the DSP program are provided to the write cache. Periodically, a block of data samples is “post-written” from the write cache to its corresponding delay line in the main memory.