Patents Represented by Attorney Kenneth R. Corsello, Esq.

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  • Addressable hierarchical metal wire test methodology
    Patent number: 7749778
    Abstract: A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chanda, Lawrence Clevenger, Timothy J. Dalton, Louis L. C. Hsu, Chih-Chao Yang
  • Method for achieving very high bandwidth between the levels of a cache hierarchy in 3-dimensional structures, and a 3-dimensional structure resulting therefrom
    Patent number: 7616470
    Abstract: A method of electronic computing, and more specifically, a method of design of cache hierarchies in 3-dimensional chips, and a cache hierarchy resulting therefrom, including a physical arrangement of bits in cache hierarchies implemented in 3 dimensions such that the planar wiring required in the busses connecting the levels of the hierarchy is minimized. In this way, the data paths between the levels are primarily the vias themselves, which leads to very short, hence fast and low power busses.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: November 10, 2009
    Assignee: International Business Machines Corporation
    Inventor: Philip George Emma