Abstract: An apparatus and method for laser ablating residue off of probe tips. In one embodiment, the probe tips of the probe needles (16) contact the test pads of an integrated circuit on a wafer (18). The probe tips build up a residue over time. This residue is due to the probe tips coming into contact with integrated circuit wafer layers such as layers (114), (120), (122), (124), and (126). This residue can be vaporized from the surface of the probe needles via exposure to a laser light. The probe needles (16) are exposed to a laser light created by a laser source (28) and ported to the probe tips by a fiber optic cable (26).

Abstract: Reflective notching of a photoresist pattern (20), generated over reflective materials on a semiconductor substrate (12), is minimized by using an anti-reflective layer (20) of silicon-rich silicon nitride. The layer of silicon-rich silicon nitride is formed over the reflective materials and a layer of photoresist is then formed over the silicon-rich silicon nitride. The photoresist layer is then photolithographically patterned to form an integrated circuit pattern (20). The silicon-rich silicon nitride layer has an absorptive index of greater than 0.25, which allows it to be used as an anti-reflective layer with photolithographic patterning systems having ultraviolet and deep ultraviolet exposure wavelengths.

Abstract: Vertically stacked regions of n-type and p-type conductivity are formed around bipolar and field effect transistors to reduce parasitic capacitance between the semiconductor device and surrounding well regions. Under reverse bias a portion of the vertically stacked region is fully depleted and thus reduces the parasitic capacitance between the semiconductor device and the well region.

Abstract: The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isolation region (40) is formed within the semiconductor substrate (12). A doped region (74, 96) is then formed such that it abuts the trench sidewall (24). A portion (56, 110) of the trench sidewall (24), abutting the doped region (74, 96), is then exposed by forming a recess (55, 112) within the trench isolation region (40). A conductive member (66, 114, 118) is then formed such that it is electrically coupled to the doped region (74, 96) along the exposed trench sidewall, as well as along the major surface (13) of the semiconductor substrate (12), and results in the formation of a low resistance contact structure.

Abstract: In one embodiment a plasma ignitor (10) having a first dielectric housing (18), that encases a first portion of a first conductive lead (14) and a first portion of a second conductive lead (16), and end cap (30), that locks its filament (31) into position, is used to initiate a plasma within an etch chamber (64). The plasma is used to etch an integrated circuit substrate (62) and to form an etched surface (78). A conductive layer of material (80) is then deposited on the etched surface (78). The first dielectric housing (18) keeps the first portion of the first conductive lead (14) and the first portion of the second conductive lead (16) from shorting to one another during processing, and the end cap (30) prevents the filament (31) from falling off during processing. Thus, the present invention allows contact resistance to be repeatably minimized.

Abstract: An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).

Abstract: A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

Abstract: Reflective notching of a photoresist pattern (20), generated over reflective materials on a semiconductor substrate (12), is minimized by using an anti-reflective layer (20) of silicon-rich silicon nitride. The layer of silicon-rich silicon nitride is formed over the reflective materials and a layer of photoresist is then formed over the silicon-rich silicon nitride. The photoresist layer is then photolithographically patterned to form an integrated circuit pattern (20). The silicon-rich silicon nitride layer has an absorptive index of greater than 0.25, which allows it to be used as an anti-reflective layer with photolithographic patterning systems having ultraviolet and deep ultraviolet exposure wavelengths.

Abstract: An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).

Abstract: In one embodiment of the invention x-rays pass through an aluminum filter (18) to form filtered x-rays. At least a portion of the filtered x-rays then pass through a portion of a x-ray mask (22) to expose a portion of a photoresist layer overlying a semiconductor substrate. The aluminum filter removes high energy photons from the x-ray spectrum that adversely effect the lithographic patterning process.

Abstract: Vertically stacked regions of n-type and p-type conductivity are formed around bipolar and field effect transistors to reduce parasitic capacitance between the semiconductor device and surrounding well regions. Under reverse bias a portion of the vertically stacked region is fully depleted and thus reduces the parasitic capacitance between the semiconductor device and the well region.

Abstract: An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define a segmented channel region (16) therebetween. A select gate electrode (18) overlies a first channel region (24) and separates the floating gate electrode (2) from the source region (12). The control gate electrode (20) overlies a third channeI region (28) and separates the floating gate electrode (22) from the drain region (14). The floating gate electrode (22) overlies a second channel region (26) and is separated therefrom by a thin tunnel oxide layer (42). The EEPROM device of the invention can be programmed by either source side injection, or by Fowler-Nordheim tunneling. Additionally, a process is provided for the fabrication of an EEPROM array utilizing adjacent select gate electrodes (18, 18') as a doping mask.

Abstract: A silicon-on insulator film (38) is formed by solid phase epitaxial re-growth. A layer of amorphous silicon (36) is formed such that it is only in direct contact with an underlying portion of a silicon substrate (12). The layer of amorphous silicon (36) is subsequently annealed to form a monocrystalline layer of epitaxial silicon (38). Because the amorphous silicon layer (36) is in contact with only the silicon substrate (12), during the re-growth process, the resulting epitaxial layer (38) is formed with a reduced number of crystal defects. The resulting epitaxial silicon layer (38) may then be used to form semiconductor devices.

Abstract: In one embodiment, delamination of a patterned silicon nitride anti-reflective layer (26) from an underlying patterned tungsten silicide layer (32), is prevented by forming a thin silicon layer (30) between the patterned tungsten silicide layer (32) and the overlying patterned silicon nitride anti-reflective layer (26).

Abstract: The reliability of integrated circuits fabricated with trench isolation is improved by increasing the thickness of the gate dielectric overlying the trench corner. After the trench isolation region (40, 56) has been formed a thin layer of silicon dioxide (44) is chemically vapor deposited over the trench isolation region (44) and the adjacent active region (23). A transistor gate electrode (46) is subsequently formed over the thin layer of silicon dioxide (44). The thin layer of silicon dioxide (44) increases the thickness of the gate dielectric that lies between the transistor gate electrode (46) and the trench corner, and therefore the breakdown voltage of the gate dielectric at the trench corner is increased.

Abstract: A semiconductor substrate (48) and a block of optical quartz (50) are simultaneously polished. An interferometer (22), in conjunction with a data processing system (16), are then used to monitor the thickness and the polishing rate of the optical quartz block. This allows the endpoint of the polishing process to be automatically and reproducibly detected, and it also allows the polishing rate of the semiconductor substrate (48) to be automatically adjusted during the polishing process.

Abstract: Defect-free field oxide isolation is achieved using a laminated layer (14) of thermal silicon dioxide and chemically vapor deposited silicon dioxide underneath a silicon nitride field oxidation mask (18). The laminated layer (14) of silicon dioxide is formed on a silicon substrate (12) and a layer of silicon nitride is then deposited over it. The silicon nitride is subsequently patterned to form a field oxidation mask (18) which defines isolation regions (22) within the silicon substrate (12). Field oxide (34) is grown in the isolation regions (22) of the silicon substrate (12) and the field oxidation mask (18) is subsequently removed.

Abstract: A conformal titanium nitride film having a preferred <111> crystal orientation is formed by chemically vapor depositing the film in two separate steps. In the first deposition step a titanium nitride layer (22) having poor step coverage and a preferred <111> crystal orientation is formed. In the second deposition step a second conformal layer of titanium nitride (24) is insitu deposited onto the first titanium nitride layer (22), wherein during the deposition the first titanium nitride layer (22) acts as a crystallographic seed layer for the second titanium nitride layer (24). As a result, a titanium nitride layer exhibiting a preferred <111> crystal orientation and good step coverage is achieved.

Abstract: A metal silicide interconnect (48, 92, 124) is formed in an integrated circuit using a sacrificial layer (30, 78, 108). In one embodiment a sacrificial layer of titanium nitride (30) is formed overlying a semiconductor substrate (12) and a polysilicon conductive member (20). The sacrificial titanium nitride layer (30) is then patterned and an underlying portion (40) of the semiconductor substrate (12), and a sidewall portion (42) of the polysilicon conductive member (20) are subsequently exposed. A metal layer (46) is deposited and then reacted with the exposed portion 40 of the semiconductor substrate (12) and the exposed sidewall (42) of the polysilicon conductive member (20) to form a metal silicide interconnect (48). The remaining portion of the sacrificial titanium nitride layer (38) is then removed after the metal silicide interconnect (48) has been formed without substantially altering the metal silicide interconnect (48).

Abstract: An input/output protection device for an integrated circuit is formed using a trench (22). A first electrode region (46) is formed adjacent a first portion of the trench sidewall (24), and a second electrode region (48) is formed adjacent a second portion of the trench sidewall (24). One of the electrode regions is then electrically coupled to an input/output pad, while the other electrode region is electrically coupled to ground. Excessive voltages on the input/output pad are then discharged when the electrode, which is electrically coupled to the input/output pad, punches through to the electrode that is electrically coupled to ground.