Abstract: Integrated circuit nonvolatile memory uses programmable resistive elements. In some examples, conductive structures such as electrodes are prepared, and the programmable resistive elements are laid upon the prepared electrodes. This prevents contamination of the programmable resistive elements from previous fabrication steps.

Abstract: In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such accesses to distinguish between logical levels. For example, the ratio of resistances characterizing input circuits of a sense amplifier and/or the read bias arrangement and/or a read reference of a memory integrated circuit is/are changed.

Abstract: Methods are described for improving the retention of a memory device by execution of a retention improvement procedure. The retention improvement procedure comprises a baking process of the memory device in a high temperature environment, a verifying process of the memory device that checks the logic state of memory cells, and a reprogramming process to program the memory device once again by programming memory cells in a 0-state to a high-Vt state. The baking step of placing the memory device in a high temperature environment causes a charge loss by expelling shallow trapped charges, resulting in the improvement of retention reliability.

Abstract: A bandgap engineered SONOS device structure for design with various AND architectures. The BE-SONOS device structure comprises a spacer oxide disposed between a control gate overlaying an oxide-nitride-oxide-nitride-oxide stack and a sub-gate overlaying a gate oxide. In one example, a BE-SONOS sub-gate-AND array architecture has multiple strings of SONONOS devices with sub-gate lines and diffusion bit lines. In another example, a BE-SONOS sub-gate-AND architecture has multiple strings of SONONOS devices with sub-gate lines, relying on the sub-gate lines that create inversions to substitute for the diffusion bit lines.

Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: Disclosed are apparatuses, methods, and manufacturing methods relating to improving data retention in nonvolatile memory. In many embodiments, reference memory corresponding to the data memory is used to determine whether to refresh the data memory.

Abstract: A two-dimensional yield map for a device, such as an integrated circuit, in a fabrication facility is computed and associated with layout data for the device in a hierarchical and/or instance-based layout file. The device has a layout including a pattern characterizable by a combination of members of a set of basis shapes. A set of basis pre-images include yield map data representing an interaction of respective members of the set of basis shapes with a defect model. A yield map for the pattern is created by combining basis pre-images corresponding to basis shapes in the combination of members that characterize the pattern to provide a combination result. The output may be displayed as a two dimensional map to an engineer performing yield analysis, or otherwise processed.