Abstract: A design structure for an integrated circuit which includes: a first flip-flop which is capable of flushing and which operates by using a first clock signal CLK 1; a second flip-flop DFF 2 which operates by using a second clock signal CLK 2, and which is connected to the first flip flop; and a third flip-flop DFF 3 which operates by using the second clock signal CLK 2, and which is connected to the first flip-flop. A test on a path between the first and second flip-flops is carried out in a manner that test data is released and captured on receipt of the clock signal CLK 2 between the second flip-flop DFF 2 and the third flip-flop DFF 3 via the first flip-flop DFF 1, and that the test data is flushed by the first flip-flop DFF 1.

Abstract: A method of removing cured conductive polymer adhesives, disclosed here as thermal interface materials, from electronic components for reclamation or recovery of usable parts of module assemblies, particularly high cost semiconductor devices, heat sinks and other module components.

Abstract: A distributed, network-based system, method, and computer program product determines an optimal allocation of available to promise components in a supply chain. An aggregate demand request is generated by a demand entity intelligent agent. The aggregate demand request is propagated via a network throughout the supply chain to a plurality of supply entity intelligent agents. The supply entity intelligent agents respond with an evaluation of available to promise supply capability. Optimal allocation of the available to promise supply is made by calculating a sequence of squared set solutions of unit demand problems using a message-based communications protocol between the demand entity and supply entity intelligent agent.

Abstract: A bonded SOI wafer and a method for forming a bonded SOI wafer are provided. According to the disclosed method, a first semiconductor wafer is provided, having a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric filled trenches extending from the outer surface inwardly into the semiconductor. The outer surface of the first wafer is bonded to the outer surface of a second semiconductor wafer to form a bonded wafer having a bulk semiconductor region, a buried dielectric layer overlying the bulk semiconductor region, and a semiconductor-on-insulator layer overlying the buried dielectric layer, with the dielectric filled trenches extending upwardly from the buried dielectric layer into the semiconductor-on-insulator layer. The thickness of the semiconductor-on-insulator layer is then reduced until uppermost surfaces of at least some of the dielectric filled trenches are at least partially exposed.

Abstract: A method for forming a bonded SOI wafer is provided in which a first wafer having a single-crystal semiconductor region has a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric filled trenches extending from the outer surface inwardly into the single-crystal semiconductor region. The outer surface of the first wafer can then be bonded to the outer surface of a second wafer having a second single-crystal semiconductor region to form a bonded wafer having a bulk single-crystal semiconductor region, a buried dielectric layer overlying the bulk single-crystal semiconductor region, and a single-crystal semiconductor-on-insulator layer overlying the buried dielectric layer. The dielectric filled trenches may extend upwardly from the buried dielectric layer into the single-crystal semiconductor-on-insulator layer.

Abstract: A method for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. The fuse link has a nominal maximum programming current and corresponding combinations of a programming voltage and a gate voltage associated with the nominal maximum programming current. A first programming current pulse is generated to provide a programming current less than the maximum programming current. The first programming current pulse causes electromigration to increase the resistance of the fuse link. A subsequent programming current pulse is applied using a combination of gate voltage and programming voltages which if applied to the fuse link absent any electromigration would result in a programming current greater than the nominal maximum programming current. However, the resistance created by the first programming pulse reduces the programming current of the subsequent programming pulse to a level below the maximum programming current.

Abstract: A system and method is provided for transmitting data signals and additional information signals having partially overlapping frequency bands simultaneously within a wire based communication system over the same wired medium using a spread spectrum technique for modulating the additional information signals.

Abstract: The Nth state of an n-stage linear feedback shift register (LFSR) used to generate pseudo random binary sequences or patterns, and which may be configured as a multiple input signature register (MISR) or single input signature register (SISR) to compress data and generate signatures, is determined by building a look-up table of n-bit states for latch positions of the linear feedback shift register; obtaining the modulo remainder of the Nth state; and generating the Nth state directly from the modulo remainder and n-bit states.

Abstract: A reworkable conductive adhesive composition, and method of making such, comprising an epoxy based conductive adhesive containing conductive metal filler particles dispersed in a solvent-free hybrid epoxy polymer matrix. In an additional embodiment an improved method of removing cured conductive polymer adhesives, disclosed here as thermal interface materials, from electronic components for reclamation or recovery of usable parts of module assemblies, particularly high cost semiconductor devices, heat sinks and other module components.

Abstract: An improved Land Grid Array interconnect structure is provided with the use of small metal bumps on the substrate electrical contact pad. The bumps interlock with segments of the fuzz button connection and increase the physical contact surface area between the contact pad and fuss button. The improved contact reduces displacement of electrical contact points due to thermo-mechanical stress and lowers the required actuation force during assembly.

Abstract: A silicon nitride spacer material for use in forming a PFET device and a method for making the spacer includes the use of a dual-frequency plasma enhanced CVD process wherein the temperature is in the range depositing a silicon nitride layer by means of a low-temperature dual-frequency plasma enhanced CVD process, at a temperature in the range 400° C. to 550° C. The process pressure is in the range 2 Torr to 5 Torr. The low frequency power is in the range 0 W to 50 W, and the high frequency power is in the range 90 W to 110 W. The precursor gases of silane, ammonia and nitrogen flow at flow rates in the ratio 240:3200:4000 sccm. The use of the silicon nitride spacer of the invention to form a PFET device having a dual spacer results in a 10%–15% performance improvement compared to a similar PFET device having a silicon nitride spacer formed by a RTCVD process.