Abstract: An integrated circuit fabrication process and transistor is provided in which salicidation is virtually eliminated from the spacer sidewall surface. Absent salicidation on that surface, bridging effects cannot occur regardless of the anneal conditions. The spacer sidewall surfaces is made substantially perpendicular to the substrate upper surface such that when a refractory metal is subsequently deposited on the semiconductor topography, the refractory metal will not accumulate on that perpendicular surface. The spacer is deposited from a specifically designed plasma enhanced chemical vapor deposition process to maintain the spacer sidewall surfaces commensurate with the gate conductor sidewall surfaces. The refractory metal is directionally deposited so that little if any metal will form on vertical surfaces and substantially all of the metal will deposit on horizontal surfaces.