Abstract: An interconnect structure is provided for converting or adapting select signals sent between a printed circuit board (PCB) and an electrical component. The interconnect structure comprises an adapter card placed between the PCB and the electrical component, wherein the adapter card includes one or more pass-through vias and non pass-through vias extending completely through the adapter card in parallel spaced relation to one another. Pass-through vias are used to couple signals having critical timing paths between the electrical component and the PCB without substantially modifying or changing the critical path switch points. The pass-through vias also provide connection of signals of non critical timing between the PCB and the component. A signal converter may be used to convert non-critical signals and place those signals at select pins upon the electrical component.

Abstract: A computer system including at least one processor and a cache subsystem, in which computer system locked cycles are generated, include a jumper assembly for operatively connecting the at least one processor and the cache subsystem so as to render locked cycles cacheable if the computer system includes only one processor and non-cacheable if the computer system includes more than one processor. A method according to the present invention includes the steps of determining whether there is one or more than one processor in a computer system, and then rendering locked cycles cacheable or non-cacheable accordingly.

Abstract: A two-computer system and method wherein data is transferred between the computers as complete disk images rather than as files. The transfer is made between the parallel ports of the two computers, for greater speed; amd RLL data compression is used to increase the effective rate of data transfer.

Abstract: A computer system having power management control features which include states of normal clock speed operation, slow clock speed operation, and stop-clock operation based on input/output activity, system bus activity, and program parameters. The system detects inactivity over a period of time and places the system in one of the states to provide for power conservation and accessibility by a user.

Abstract: A liquid crystal display (LCD) of high visual quality and having a high density wiring arrangement is provided. The LCD can accommodate up to four addressing and/or control conductors placed across the display and between columns and rows of display electrodes. If four conductors are utilized, those conductors can be arranged as a stacked pair placed between rows and a stacked pair placed between columns of display electrodes. At areas where one stacked pair of conductors intersect the other, a plurality of cross-over regions exists which provide vias for routing the conductors through the region as well as for connecting the conductors to a control circuit within each region. Each control circuit includes a pass-gate transistor for receiving two addressing conductors and a memory element capable of receiving two power conductors.