Abstract: A method and a system are provided for forming a borderless contact structure. In particular, a method is provided which includes using an inorganic anti-reflective coating layer as an etch stop to form a borderless contact structure. In some embodiments, the method may include patterning an interconnect line above an inorganic layer with anti-reflective properties and depositing an upper interlevel dielectric layer above the interconnect line. A trench may then be etched within the upper interlevel dielectric layer such that a borderless contact structure may be formed in contact with said interconnect line. Consequently, a semiconductor topography is provided, in such an embodiment, which includes an inorganic anti-reflective coating layer arranged below an interconnect line and a contact structure arranged upon the interconnect line. In some embodiments, a width of the contact structure may be greater than a width of the interconnect line.

Abstract: A circuit, method, and network are disclosed herein to implement a voltage-controlled LC oscillator. The oscillator is configured having an LC tank circuit which is modulated by an in-phase modulating voltage. The modulating voltage can have a phase angle and amplitude that is controlled. Depending on the values of those control signals, the oscillating voltage will either increase or decrease current within the LC tank circuit and, thereby, increase or decrease the oscillating voltage respectively. Any number of phases can be connected together to produce signals of dissimilar phase angles. Preferably, those signals have phase angles of 0°, 180°, or even fractions thereof if an external circuitry is applied to the oscillation network.

Abstract: The present invention includes a circuit, system, and method for avoiding a non-desired output from a latch, and a selector circuit that is programmable to select an input to a prioritizer which, based on that input, sets the latch output to avoid a non-desired state regardless of the latching input values. The embodiments described herein are useful in forming a non-clocked latch that employs set and reset inputs, and thus, may be an SR latch. The SR latch is envisioned having either MOSFET or bipolar transistors, and can be employed either having only NMOS transistors, only PMOS transistors, or CMOS transistors. The latch also includes an improved selector circuit that is easily programmed to configure the latch in either a set-dominant, a reset-dominant, or a memory-dominant configuration based solely on the voltage values fed to the latch by the selector circuit. As such, the selector circuit of the present invention embodies an improved programmability over previous circuits.