Abstract: A reduced permittivity interlevel dielectric in a semiconductor device arranged between two levels of interconnect. The dielectric comprises a first dielectric layer preferably from a silane source deposited on a first level interconnect to form air gaps at midpoints between adjacent first interconnect structures, a second dielectric containing air gap trenches at spaced intervals across the second dielectric, and a third dielectric formed upon said second dielectric. A second interconnect level is formed on the third dielectric.
Type:
Grant
Filed:
January 27, 1998
Date of Patent:
March 27, 2001
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Basab Bandyopadhyay, H. Jim Fulford, Jr., Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan