Abstract: An error correction code for single symbol error correction and double symbol error detection is generated according to a novel modular H-matrix. The H-matrix utilizes a modular design with multiple iterations of a plurality of subsets. In particular, one example of this H-matrix includes a plurality of rows and columns with each of at least one row of the H-matrix comprising, in part, multiple iterations of one subset of the plurality of subsets. The remainder of the rows, comprises, in part, a cyclic permutation of all of the remaining subsets of the plurality of subsets.

Abstract: A capping structure and capping method are presented for an electronics package having a substrate and one or more electronics devices disposed on the substrate. The capping structure includes a capping plate sized to cover the electronics device(s) disposed on the substrate, and two or more force transfer pins. The force transfer pins are disposed between the capping plate and the substrate so that when a force is applied to the capping plate or the substrate, the force is transferred therebetween via the force transfer pins. Various capping plate and pin configurations are presented.

Abstract: An object of the present invention is to inform a person who adjusts the direction of an antenna 70 of the intensity of a signal received by the antenna 70 without connecting or adding special equipment to the antenna 70 or a connection cable 74. The satellite receiver 20 comprises: a received intensity information outputting means 22 for outputting received intensity information describing the intensity of a signal received from the antenna 70; a modulating means 30 for superimposing the received intensity information on a carrier wave; and a superimposing means 40 for superimposing the carrier wave carrying the received intensity information on a connection cable 74.

Abstract: Data is protected during conversion from one or more source error correction codes to one or more destination error correction codes by generating check bits of the destination error correction codes prior to a detection for errors in the source error correction codes. After commencing generation of these check bits, a detection is made for any errors in the source error correction codes. These errors are subsequently corrected in the destination error correction codes by complementing the erroneous bits of the destination error correction code. In addition, various logic reduction techniques may also be implemented to increase efficiency.

Abstract: Uncorrectable errors are detected during the transmission of a data word according to an error correction code. Then, any address faults are identified from among the detected uncorrectable errors. In addition, address faults as well as uncorrectable memory data failures are detected from among the detected uncorrectable errors. Furthermore, address parity bits are not required to be stored to memory.

Abstract: A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames.

Abstract: Described is a method for minimizing switching noise in the high- and mid-frequency range on printed circuit cards or boards by means of a plurality of surface mounted decoupling capacitors. A novel configuration and implementation of capacitor pads including the connecting vias is also presented. As a result the parasitic inductance of the pads and vias can be significantly reduced. Thus the effectiveness of the decoupling capacitors in the mid and high frequency range can be increased, the voltage drop can be reduced and the system performance can be increased. Several design rules for the new pad via configuration lead to the significant reduction of the parasitic inductance. The proposal is especially important for high integrated system designs on boards and cards combined with increased cycle times.

Abstract: An optical waveguide, radiation emitting device employing the same, and process for fabricating the radiation emitting device are provided. The optical waveguide has a core fabricated of a first material with a first index of refraction and cladding surrounding the core fabricated of a second material with a second index of refraction. The core is an active material which emits radiation at a desired wavelength when pumped with radiation of a predetermined wavelength, and the first material and second material are dissimilar materials, having been separately fabricated and subsequently physically assembled as the waveguide.

Abstract: Cavity plate and jet nozzle assemblies are presented for use in cooling an electronic module. The assemblies include a cavity plate having one or more blind holes formed therein and one or more jet nozzles each configured to reside within a respective blind hole of the cavity plate. A lower surface of the blind hole and/or jet nozzle is curved to facilitate the flow of fluid from the blind hole after impinging upon the lower surface of the blind hole. Various jet nozzle configurations are also provided which employ pedestals or radially extending fins. Further, the radially extending fins may interdigitate with inwardly extending fins on the inner sidewall of a respective blind hole in the cavity plate. Methods of fabricating the cavity plate and jet nozzle assemblies are also presented.

Abstract: Structures and methods are provided for absorbing stress between a first electrical structure and a second electrical structure connected together, wherein the first and second structures have different coefficients of thermal expansion. A dielectric material is disposed on at least one of the first and second electrical structures. This dielectric material is a low modulus material which has a high ultimate elongation property (LMHE dielectric). Preferably, the LMHE dielectric has a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least 20 percent. The LMHE dielectric can be photo patternable to facilitate formation of via openings therein and a metal layer is formed above the LMHE dielectric which has conductors capable of expanding or contracting with the dielectric.

Abstract: An information gathering facility is provided to gather information on a state of a computer system. The information gathering facility includes a dictionary file data structure having at least one inquiry which comprises at least one instruction to call a pre-existing executable on the computer system. The pre-existing executable is executed in response to processing of the at least one instruction and data is obtained from the executable. This data is used in accordance with the at least one instruction to derive a result to be included as part of the state information on the computer system.

Abstract: A thermal dissipation subassembly is provided for an electronic device. The subassembly includes a thermal spreader configured to thermally couple to a surface of a heat generating component of the electronic device. The heat generating component, e.g., an integrated circuit chip, has a non-uniform thermal distribution across the surface thereof between at least one first region of the surface and at least one second region of the surface, with the at least one first region having a higher heat flux than the at least one second region. The subassembly further includes at least one thermoelectric device aligned to at least a portion of each first region having the higher heat flux, wherein the at least one thermoelectric device facilitates dissipation of the higher heat flux. In one embodiment, one or more thermoelectric devices are embedded within the thermal spreader and thermally isolated therefrom.

Abstract: The invention relates to a testable on-chip capacitor cell 10 including a decoupling capacitor (Ci) which can be disconnected from the power distribution network and discharged through a cell internal discharge circuit. An externally controllable switch (Si) connects in a first switching position the decoupling capacitor to the power supply system and disconnects in a second switching position the decoupling capacitor from the power supply system and connects it to a resistor (Ri) which is part of the discharge circuit. An off-chip control unit (16) is provided for toggling the switch with a frequency fT between its first and second position to perform a capacitor test operation. By a current measurement device the averaged power supply current demand of the decoupling capacitor is measured when switch (Si) is toggled. The actual capacity of the decoupling capacitor is determined as a function of the power supply voltage, of the switch toggling frequency (fT) and of the averaged power supply current measured.

Abstract: A write-behind computer program product is presented which allows writing data to multiple volumes of storage media associated with one or more server nodes in a distributed processing environment. A client application on a client node writes blocks of data to a first magnetic tape of a first server node until an end of physical storage of the first magnetic tape is reached, without having predetermined the size of the first magnetic storage. Thereafter, the writing of blocks of data is switched to a second magnetic tape, which may be on the first server node or a second server node in the system. The writing and switching process can repeat a number of times across multiple magnetic tapes. Data is written in a write-behind operation and the switching to a new magnetic tape occurs transparent to the client application, and without loss of data.

Abstract: Characterization of free-space electromagnetic energy pulses (15) using a chirped optical probe beam is provided. An electro-optic or magneto-optic crystal (14) is positioned such that the free-space radiation and chirped optical probe signal co-propagate, preferably in a co-linear common direction, through the crystal where a temporal waveform of the free-space radiation is linearly encoded onto a wavelength spectrum of the chirped optical probe signal. The temporal waveform of the free-space radiation is then reconstructed using, for example, a dynamic subtraction of the spectral distribution of the chirped optical probe signal without modulation from the spectral distribution of the chirped optical probe signal with modulation by the free-space radiation.

Abstract: A computer display system, method and article of manufacture are presented allowing a user to interactively arrange two-dimensional windows for display in three dimensions on a two-dimensional display screen of the computer system. A window manager associated with the display screen is configured to respond to a user's selection of a frame edge of a window, e.g., using a third mouse button, by rotating the window from a two-dimensional depiction to a three-dimensional depiction. Rotation of the window occurs on an edge frame opposite to the selected edge frame and the rotation angle is related to the magnitude that the user drags the pointing device after selection of one edge frame of the window to be swung. In a similar manner, a pointing indicator is superimposed within the rotated window for tracking within the rotated coordinates of the window in response to user manipulation of an associated pointing device.

Abstract: A checkpoint of a parallel program is taken in order to provide a consistent state of the program in the event the program is to be restarted. Each process of the parallel program is responsible for taking its own checkpoint, however, the timing of when the checkpoint is to be taken by each process is the responsibility of a coordinating process. During the checkpointing, various data is written to a checkpoint file. This data includes, for instance, in-transit message data, a data section, file offsets, signal state, executable information, stack contents and register contents. The checkpoint file can be stored either in local or global storage. When it is stored in global storage, migration of the program is facilitated. When a parallel program is to be restarted, each process of the program initiates its own restart. The restart logic restores the process to the state at which the checkpoint was taken.

Abstract: A cooling system and method of fabrication are provided for cooling an electronics device. The cooling system includes a cooling unit and an evaporator plate having at least one isolated refrigerant loop therein for receiving coolant from the cooling unit. A thermal buffer unit having a phase change material therein is thermally coupled to the evaporator plate to maintain temperature of the evaporator plate within a predefined range for a period of time upon failure or shut down of the cooling unit. A thermal conductor structure, such as a metal foam structure and/or thermal transfer rods, is disposed within the thermal buffer unit to facilitate heat transfer between the phase change material and the evaporator plate.

Abstract: A thermal dissipation assembly is provided for an electronic device. The assembly includes a thermal spreader configured to thermally couple to a surface of a heat generating component of the electronic device. The heat generating component, e.g., an integrated circuit chip, has a non-uniform thermal distribution across a surface thereof between at least one first region of the surface and at least one second region of the surface, with the at least one first region having a higher heat flux than the at least one second region. The assembly further includes a thermal interface for attaching to the surface of the thermal spreader and aligning to contact a portion of the surface of the heat generating component when the thermal dissipation assembly is placed in contact therewith. The thermal interface is patterned to cover only a portion of the surface of the heat generating component to selectively thermally couple the thermal spreader to the surface of the heat generating component.

Abstract: Chips first packaging structures and methods of fabrication are presented which employ electroless metallizations. An electroless barrier metal is disposed over and in electrical contact with at least one aluminum contact pad of the chips first integrated circuit. The electroless barrier metal is a first electroless metal and is a different material than the at least one aluminum contact pad. An electroless interconnect metal is disposed above and electrically contacts the electroless barrier metal. The electroless interconnect metal is a second electroless metal, which is different from the first electroless metal. As an example, the electroless barrier metal comprises electroless nickel and the electroless interconnect metal comprises electroless copper.