Patents Represented by Attorney, Agent or Law Firm Kilworth, Gottman, Hagan & Schaeff, L.L.P.
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Patent number: 6573652Abstract: An encapsulated display device. The device includes a substrate, an environmentally sensitive display device adjacent to the substrate, and at least one first barrier stack adjacent to the environmentally sensitive display device. The barrier stack encapsulates the environmentally sensitive display device. It includes at least one first barrier layer and at least one first polymer layer. The encapsulated display device optionally includes at least one second barrier stack located between the substrate and the environmentally sensitive display device. The second barrier stack includes at least one second barrier layer and at least one second polymer layer. A method for making an encapsulated display device is also disclosed.Type: GrantFiled: April 20, 2000Date of Patent: June 3, 2003Assignee: Battelle Memorial InstituteInventors: Gordon Lee Graff, Peter Maclyn Martin, Mark Edward Gross, Ming Kun Shi, Michael Gene Hall, Eric Sidney Mast
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Patent number: 6498210Abstract: The silylated polyurethane polymer includes a polyurethane prepolymer having between greater than about 50 to about 95% of NCO groups terminated with silane capping agents. The polymer has an improved mechanical properties. The polymer can also have between about 5% to less than about 50% of the NCO groups terminated with low molecular weight terminators.Type: GrantFiled: July 13, 2000Date of Patent: December 24, 2002Assignee: Adco Products, Inc.Inventors: Xiaobin Wang, Scott D. Kubish, Brian J. Briddell
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Patent number: 6417695Abstract: A semiconductor die is provided with an internally programmable router to assign signal paths to select connection points. A switching matrix incorporating at least one antifuse is utilized to selectively route signal paths on the semiconductor die. The chips can then be used individually, for example to reconfigure chip pin assignments to operate in a plurality of different socket layouts, or where features or controls of a chip are selectively enabled or disabled. A further alternative involves programming a first chip, then stacking piggyback, or one on top of the other, the first chip onto a second chip. The contact pins are electrically coupled together, thus avoiding the need for external frames and pin rerouting schemes to form stacked chips. In the stacked chip configuration, control pins are rerouted to align with unused pins on the chip stacked against.Type: GrantFiled: March 15, 2001Date of Patent: July 9, 2002Assignee: Micron Technology, Inc.Inventor: Kevin Duesman
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Patent number: 6294464Abstract: A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide.Type: GrantFiled: March 10, 2000Date of Patent: September 25, 2001Assignee: Micron Technology, Inc.Inventor: Jigish D. Trivedi
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Patent number: 6254007Abstract: A security document is prepared by designating specialized tiling elements to be printed in selected image element cells across the face of the document. In accordance with one embodiment of the present invention, a method of preparing a security document is provided comprising the steps of: (i) designating a security image area on a face of a document; (ii) dividing the security image area into a plurality of image element cells, such that the image element cells define an array of image element cells across the security image area; and (iii) designating respective printed tiling elements to be printed in selected ones of the image element cells to define a printed security image and a printed complementary security image within the security image area. Individual ones of the respective printed tiling elements comprise printed units positioned within the respective image element cells.Type: GrantFiled: February 2, 2000Date of Patent: July 3, 2001Assignee: The Standard Register CompanyInventor: William H. Mowry, Jr.
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Patent number: 6217964Abstract: An endless belt for use in digital imaging systems is provided having uniform edge to edge flatness, and precise circumferential and edge to edge thickness. The layers comprising the belt may be tailored as desired for use in either latent image formation, image transfer or sheet transport operations. In one embodiment, the belt includes an elastomeric base layer, an intermediate polymer ply over the base layer, and an outer elastomeric layer. Alternatively, the belt includes an elastomeric base layer and an outer polymer layer. The belt may further include reinforcing layers which may comprise a woven or non-woven fabric layer and/or an elastomerimpregnated spun cord layer. The belt is preferably manufactured by building the layers on a workpiece and then curing the layers.Type: GrantFiled: February 24, 1999Date of Patent: April 17, 2001Assignee: Day International, Inc.Inventors: Sylvain L. Ndebi, William Haul Haddock, Allen T. Shannon
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Patent number: 6047471Abstract: A process is provided for forming a resistance welding electrode. The process includes the step of providing a billet formed from a high conductivity metal. The billet includes a first portion having a first inner cavity formed therein. The process further includes the steps of inserting an insert into the first inner cavity of the billet, and deforming the insert so as to mechanically lock the insert in place in the billet. The deformed billet comprises the resistance welding electrode.Type: GrantFiled: November 20, 1997Date of Patent: April 11, 2000Assignee: The Nippert CompanyInventors: Russell Alan Nippert, Brian Eugene Swank