Abstract: In one embodiment, a method and apparatus for triggering and capturing digital circuit signals are disclosed. For example, a logic analyzer according to one embodiment includes at least one trigger combination block and a state machine deploy in a memory coupled to the trigger combination block, where the state machine includes an input coupled to an output of the trigger combination block and an output coupled to a capture memory in which one or more digital circuit signals are stored.

Abstract: In one embodiment, a device is disclosed. For example, in one embodiment of the present invention, the device comprises a memory core having a shared buffer, and an arbitration logic module for receiving a destination ready signal from a processing source of a plurality of processing sources. The device also comprises at least one pipeline stage for storing at least one piece of data read from the shared buffer, and at least one matching pipeline stage storing at least one valid signal associated with the at least one piece of data read from the shared buffer. The device also comprises a counter for storing a value, wherein the value represents a number of pieces of data read from the shared buffer, but have not been delivered to the processing source.

Abstract: In one embodiment, a monitor circuit is disclosed. For example, the monitor circuit includes a first delay line circuit having a plurality of delay taps for receiving data from a data channel, and a second delay line circuit having a plurality of points for sampling the data received from the first delay line circuit, where the plurality of points comprises an input point, a middle point and an output point. The monitor circuit further includes a voltage control circuit for providing a control voltage to the second delay line circuit, and a data compare circuit for comparing a data value of the input point and a data value of the middle point to produce a first out-of-bounds signal, and for comparing the data value of the middle point and a data value of the output point to produce a second out-of-bounds signal.

Abstract: A method and apparatus for dividing clock frequencies are disclosed. For example, a circuit according to one embodiment of includes a high-speed divider and a plurality of programmable dividers cascading with the high-speed divider, wherein the plurality of programmable dividers are of a lower speed than the high-speed divider.

Abstract: In one embodiment, an integrated circuit for providing distributed temperature sensing is disclosed. For example, the integrated circuit comprises a plurality of circuit components, an internal temperature sensing device deployed among the plurality of circuit components; and a plurality of ring-oscillators deployed among the plurality of circuit components, wherein at least one of the plurality of ring-oscillators is deployed adjacent to the internal temperature sensing device, where the plurality of ring-oscillators is used to provide one or more temperature measurements, e.g., a temperature gradient, for the integrated circuit.

Abstract: A method and apparatus for dynamically aligning high-speed signals in an integrated circuit are disclosed. For example, an integrated circuit according to one embodiment includes a logic fabric and at least one input/output interface coupled to the logic fabric. The input/output interface includes a plurality of input/output sites and an edge detector coupled to the plurality of input/output sites for detecting an edge in an input signal received by the integrated circuit. A plurality of delay lines are used to determine whether the input signal arrives too early or too late compared to a clock signal in the integrated circuit, and delays in the delay lines are adjusted to align the input signal with the clock signal in the integrated circuit.

Abstract: In one embodiment, a method and apparatus for configuring the internal memory cells of an integrated circuit through the logic fabric are disclosed. For example, an integrated circuit according to one embodiment includes a logic fabric and a plurality of input/output blocks coupled to the logic fabric, wherein the plurality of input/output blocks is positioned around the periphery of the logic fabric. The plurality of input/output blocks therefore forms a ring around the logic fabric, wherein a data path and a clock path are formed along the periphery of the logic fabric through the plurality of input/output blocks.

Abstract: In one embodiment, a method and apparatus for shifting the bits of a data word are disclosed. For example, a deserializer according to one embodiment includes an input register bank for capturing serial data comprising n bits, an intermediate register bank, and a strobe mux coupled to an input of the intermediate register bank. An input of the intermediate register bank is coupled to an output of the input register bank. The strobe mux comprises a single multiplexer configured to select a bitslip strobe signal that controls an order in which the n bits of the serial data are captured in the intermediate register bank.

Abstract: A method and apparatus for aligning the phases of digital clock signals are disclosed. For example, a phase alignment circuit according to one embodiment includes a frequency adjuster comprising a first plurality of inputs, where at least some of the first plurality of inputs are coupled to an output of a digital clock of an integrated circuit, a phase adjuster comprising a second plurality of inputs, where at least some of the second plurality of inputs are coupled to a plurality of outputs of the frequency adjuster, and an XOR gate comprising a third plurality of inputs, each of the third plurality of inputs being coupled to one of the plurality of outputs of the frequency adjuster.

Abstract: In one embodiment, an integrated device is disclosed. For example, in one embodiment of the present invention, a device comprises a core module for providing one or more output signals. The device comprises an output logic module for receiving the one or more output signals and an input logic module, wherein the one or more output signals are received by the input logic module via one or more feedback paths, where the one or more output signals are forwarded back to the core module.

Abstract: In one embodiment, an integrated device is disclosed. For example, in one embodiment of the present invention, a device comprises a logic control, and a combination differential driver coupled to the logic control, wherein the logic control receives a control signal for configuring the combination differential driver as a Low Voltage Differential Signaling (LVDS) driver or as a Transition Minimized Differential Signaling (TMDS) driver.

Abstract: A configuration management system is disclosed. For example, an embodiment of the present invention provides a configuration management system comprising a configuration storage device containing configuration data, and an integrated circuit, coupled to the configuration storage device, where the integrated circuit comprising at least one configuration management controller for managing a configuration of the integrated circuit in accordance with the configuration data, where the integrated circuit is deployed in a radiation tolerant device.

Abstract: A test methodology for testing a memory device with a RSR feature is disclosed. For example, a method for testing a memory device having at least one memory cell group, at least one redundant memory cell group, and a defect detect register is disclosed. In one embodiment, the method applies at least one memory test to the at least one memory cell group; and applies a defect detect register test to the defect detect register.

Abstract: A configuration management system is disclosed. For example, an embodiment of the present invention provides a configuration management system comprising at least one configuration storage device containing configuration data, and a plurality of integrated circuits, coupled to said at least one configuration storage device, where the plurality of integrated circuits are coupled in a loop, where each of the plurality of integrated circuits comprising at least one configuration management controller for managing a configuration of another integrated circuit in the loop in accordance with the configuration data, where the plurality of integrated circuits is deployed in at least one radiation tolerant device.

Abstract: Method and apparatus for configuring a programmable logic device to operate at a plurality of clock frequencies comprising configurable programmable self-timed delay circuits and associated configuration software. The configurable IC clock frequencies increase device performance and manufacturing yield.

Abstract: A bootstrapping circuit capable of sampling input signals beyond a supply voltage is disclosed. In one embodiment, the bootstrapped circuit is implemented having a reduced area and/or power consumption requirement.

Abstract: The present invention provides systems and methods of cross-domain access control in which a client node (250) sends a request (250) for a resource to a resource server (260). In response, a local proxy server (270) automatically obtains a ticket having a revocation status (275) and forwards the ticket (275) to an authorization server (280) that communicates with the resource server (260) regarding access.

Abstract: An electrically adjustable phase-shifting device is arranged on a substrate comprising at least a first waveguide designed for guiding optical signals and a thermoelectric element arranged adjacent to the first waveguide in order to shift the phase of an optical signal in the first waveguide by means of a thermo-optic effect according to a control voltage applied to the thermoelectric element. In one embodiment, the thermoelectric element is a Peitier element which comprises at least first and second electrically conducting segments which are serially connected, the first and second elements alternating consecutively.

Abstract: An apparatus and a concomitant method for portably detecting and recognizing text information in a captured imagery. The present invention is a portable device that is capable of capturing imagery and is also capable of detecting and extracting text information from the captured imagery. The portable device contains an image capturing sensor, a text detection module, an OCR module, a storage device and means for presenting the output to the user or other devices.

Abstract: A method and apparatus for predicting analytically the probability of closing a sale. The apparatus comprises a general purpose computer having a central processing unit (CPU) and a memory for generating sales probabilities. An operating system and sales probability engine are loaded from a storage medium and executed in the memory. The sales probability engine utilizes various sales information to determine the account control level corresponding to a particular stage of the sales cycle. A sales probability is then derived by applying the account control level and the current stage of the sales cycle as indices to a sales probability look-up table.