Abstract: A method for fabricating a semiconductor device to enlarge a channel region is provided. The channel region is enlarged due to having pillar shaped sidewalls of a transistor. The transistor includes a fin active region vertically protruding on a substrate, an isolation layer enclosing a lower portion of the fin active region, and a gate electrode crossing the fin active region and covering a portion of the fin active region. An isolation layer is formed enclosing a lower portion of the fin active region and the isolation layer under the spacers is partially removed to expose a portion of the sidewalls of the fin active region. Subsequently, dry etching is performed to form the sidewalls having a pillar/neck.

Abstract: For an integrated circuit associated with a plurality of parameters whose values are described by a first probability distribution function, a method for estimating a failure probability includes selecting a first plurality of samples, performing a first test to determine an outcome for each of the first plurality of samples and identifying failed samples, and clustering the failed samples using a computer-implemented cluster forming method that, in some cases, returns multiple clusters. The method also includes forming a probability distribution function for each of the clusters, forming a composite probability distribution function that includes a weighted combination of the first probability distribution function and the probability distribution function for each of the clusters. The method further includes selecting a second plurality of samples using the composite probability distribution function and performing a second test to determine an outcome for each of the second plurality of samples.