Patents Represented by Attorney, Agent or Law Firm Kirk Cesari
  • Patent number: 6765737
    Abstract: A disc drive includes a base and a disc rotatably attached to the base. The disc has an inner diameter and an outer diameter and a plurality of tracks. Information is written on the plurality of tracks. The plurality of tracks are written at a variable track pitch. The tracks positioned near the outer diameter are wider in pitch than the tracks positioned near the inner diameter. The plurality of tracks further include a first group of tracks written at a first track pitch, and a second group of tracks written at a second track pitch. The track pitch of each of the first group and the second group of tracks is selected such that the percentage of track misregistration for each group will be substantially the same. This method provides a means to increase storage capacity for a predetermined track misregistration budget.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: July 20, 2004
    Assignee: Seagate Technology LLC
    Inventors: Choonkiat Lim, Xiong Liu, Joseph Cheng-Tsu Liu, Kevin A. Gomez
  • Patent number: 6421759
    Abstract: The present invention relates generally to the field of disc controllers, and more specifically to an efficient buffer manager for a disc controller. A state machine in the buffer manager is provided which is responsive to a clock controlled by a single frequency base clock signal and a speed selection signal which indicates the speed of the buffer memory and which is designed to provide a base clock signal for the state machine having a fixed base period and an extended second portion of the cycle period which is extended to reflect the time of the RAMs cycle, plus the necessary time to allow for circuit delays and the like. Thus, different speed RAMs can be used in association with the buffer manager designed in this manner, while always controlling access for reading and writing to the RAM during a single complete cycle of the buffer manager. This allows for direct gating of all control signals to the buffer RAM, simplifying the design of the buffer memory controller and its associated logic.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: July 16, 2002
    Assignee: Seagate Technology LLC
    Inventor: Gregory P. Moller
  • Patent number: 6393598
    Abstract: The present invention provides sequence detection which takes into account amplitude and/or time distortions caused by neighboring magnetization regions on the magnetic medium, wherein the distortions in one magnetization region are caused by the closeness of neighboring magnetization transitions on one or both sides thereof. The sequence detection according to the present invention provides an extended state diagram to include the effects of leading and/or trailing magnetization transitions. More particularly, it has been found that accounting for the effects of trailing transitions requires an increase in the number of states in the state diagram used to form the Viterbi detector. Leading transitions are neutralized by increasing the number of branches between states in the Viterbi detector. Increasing the number of branches instead of states keeps the complexity low and thus saves hardware and associated costs.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: May 21, 2002
    Assignee: Seagate Technology LLC
    Inventors: Kinhing P. Tsang, Robert E. Kost, Kenneth R. Burns
  • Patent number: 6351822
    Abstract: In a computer data storage system configured for patching Read Only Memory (ROM) by remapping data sections, the ROM containing a token to define the start of each one of the data sections and a patch existing for at least one of the data sections, the patch providing additional data at the start of the data section; whereby the patch is included in one of the data sections when an access to one of the data sections is initiated at the token. The patch further optionally replaces at least a part of one of the data sections. The patch may be in writeable memory and if so, the ROM appears writeable thereby. The indicator will normally be a software No Operation or non-destructive instructive, since a No Operation instruction (NOP) causes a one cycle pause in the processor and allows time for the patch to be smoothly integrated.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: February 26, 2002
    Assignee: Seagate Technology LLC
    Inventors: John Marc Wright, John Chester Masiewicz