Abstract: A fault tolerant network architecture employs a network node including a first network interface to an addressable network. The first network interface is assigned a first network interface IP address defined by a first IP address range. The network node also includes at least one virtual IP address defined by an IP address range outside of the first IP address range. At least one virtual address is advertised to the addressable network from the first network interface, and packets addressed to the at least one virtual IP address can be routed to the first network interface.
Type:
Grant
Filed:
October 27, 2004
Date of Patent:
November 11, 2008
Assignee:
Morgan Stanley
Inventors:
Anthony Golia, J. Rambhaskar, Thomas Schwarz
Abstract: A method of preparing 2,5-bis(hydroxymethyl)tetrahydrofuran comprises heating a reaction mixture comprising 2,5-(hydroxymethyl)furaldehyde, an organic solvent, and a catalyst system comprising nickel and zirconium at a temperature, for a time, and at a pressure sufficient to promote reduction of the 2,5-(hydroxymethyl)furaldehyde to 2,5-bis(hydroxymethyl)tetrahydrofuran to produce a product mixture comprising 2,5-bis(hydroxymethyl)tetrahydrofuran.
Abstract: A medical delivery system for delivering or retrieving a medical implant. In one embodiment, the medical delivery system includes a tube having a lumen; an implant; and a suture releasably joined to the implant, the suture comprising a first end, a second end, and a releasable knot, wherein tension applied to the first end of the suture collapses at least a portion of the implant for introduction into the tubular lumen and tension applied to the second end of the suture releases the implant.
Abstract: Process for obtaining lignan from plant material by extraction with an extraction solvent and separation of the liquid fraction from the plant material. The separated liquid fraction containing the lignan product is subjected to further processing to remove cyanogenic sugars and other impurities. The resulting lignan containing product may be formulated for the treatment of various conditions, such as cancer, diabetes, hypertension, lupus, and atherosclerosis.
Type:
Grant
Filed:
June 4, 2004
Date of Patent:
August 5, 2008
Assignee:
Archer-Daniels-Midland Company
Inventors:
Rishi Shukla, Ahmad K. Hilaly, Kevin M. Moore
Abstract: In one aspect, the invention relates to a method for analyzing qualitative data. The method includes the step of providing a plurality of evaluation categories and a respective ranking system. Providing a closed curvilinear graph in which each unit of radius corresponds to a rank in the ranking system is another step of the method. Another step in the method includes placing each evaluation category at a location on the circumference of the closed curvilinear graph. The steps of the method also include providing the evaluation categories and ranking system to an entity being evaluated. The entity selects a rank in response in each respective category according to the method. Plotting the ranking of each respective category as a node in the closed curvilinear graph in response to the ranking by the entity is another step in the method.
Type:
Grant
Filed:
September 10, 2004
Date of Patent:
August 5, 2008
Inventors:
Phillip W. Lawson, Jr., Robert L. Lindstrom
Abstract: The invention relates to the use of the metrology methods and the related apparatus disclosed herein that incorporate thermal treatment devices and methods that improve defect detection. Specifically, in one aspect the invention relates to method of thermally treating a semiconductor wafer such that an acceleration of interstitial defect migration is achieved while leaving vacancy defects substantially unaltered.
Abstract: A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.
Type:
Grant
Filed:
April 29, 2005
Date of Patent:
July 15, 2008
Assignee:
Taiwan Semiconductor Manufacturing Company Ltd.
Abstract: A method of preparing 2,5-bis(hydroxymethyl)tetrahydrofuran comprises heating a reaction mixture comprising 2,5-(hydroxymethyl)furaldehyde, an organic solvent, and a catalyst system comprising nickel and zirconium at a temperature, for a time, and at a pressure sufficient to promote reduction of the 2,5-(hydroxymethyl)furaldehyde to 2,5-bis(hydroxymethyl)tetrahydrofuran to produce a product mixture comprising 2,5-bis(hydroxymethyl)tetrahydrofuran.
Abstract: A sense amplifier for detecting a logic state of a selected electrical fuse cell among a number of unselected electrical fuse cells includes a bias module coupled to a power supply for generating a first current, and a tracking module coupled to the bias module for generating a second current. A current supplier is coupled to the bias module and the tracking module for generating a third current substantially equal to a sum of the first and second currents scaled by a predetermined factor, the third current being diverted into a first sub-current flowing through the selected electrical fuse cell and a second sub-current leaking through the unselected electrical fuse cells. The tracking module is so configured that the second current scaled by the predetermined factor is substantially equal to the second sub-current, thereby avoiding the first sub-current to be reduced by the second sub-current.
Abstract: A SRAM device includes at least one memory cell having a source line for receiving an internal supply power, and a voltage management circuit coupled to the source line for generating the internal supply power that varies in at least two different voltage levels, depending on various operation modes of the memory cell.
Abstract: Germicidal compositions containing phenylmalonaldehyde-type compounds, or mixtures of phenylmalonaldehyde-type compounds and phthalaldehydes, and methods of using such compositions for killing bacteria, disinfection, or sterilization, are disclosed. In one aspect, a germicidal composition may include a diluent, and a germicidal compound having the formula: wherein Ar is an aryl group that is selected from the group consisting of phenyl, 4-pyrimidinyl, and 2-(2-nitro-3-formyl-phenyl). In a further aspect, the composition may also include a germicidal efficacy enhancer such as isophthalaldehyde or a combination of isophthalaldehyde and terephthalaldehyde.
Abstract: Alloy tool steels of the present invention may be suitable for metalworking tools, bearings, gears, and specialized automotive parts, such as camshafts and lifters. A steel alloy, comprising: by weight, 0.5 to 1% carbon; 0.5 to 2.0% vanadium; 1.0 to 2.0% aluminum; 0.2 to 1.0% silicon; chromium; molybdenum; manganese; and iron. Further embodiments of the alloy tool steel consisting essentially of: by weight, 0.5 to 1% carbon; 0.5 to 1.5% vanadium; 1.0 to 2.0% aluminum; 0.2 to 1.0% silicon; 3.5 to 4.5% chromium; 0.1 to 0.5% manganese; 3.5 to 4.5% molybdenum; less than 0.05% nitrogen and the balance iron. In certain embodiments, the alloy tool steel comprises a ratio of the weight percentage of aluminum to the weight percentage of silicon in the range of 1.7 to 2.2.
Abstract: A method for testing a memory with cell plates and bit-line plates comprises putting the memory in a test mode, applying a test pattern to the memory, then providing a first voltage higher than Vdd/2 to the cell plate when writing a ‘1’ to a predetermined cell, providing a second voltage lower than Vdd/2 to the cell plate when writing a ‘0’ to a predetermined cell, wherein the first and second voltages are applied to emulate weak charge storage in the memory cell, similarly, providing a third voltage higher than Vdd/2 to the bit-line plate when expecting to read a ‘1’ from a predetermined cell, and providing a fourth voltage lower than Vdd/2 to the bit-line plate when expecting to read a ‘0’ from a predetermined cell, wherein the third and fourth voltages are applied to emulate charge decay in the memory cell.
Abstract: Embodiments of a leveler that may be controlled by a computer are provided. The leveler may include a top frame that has at least a first set of rolls mounted thereon. The top frame includes a plurality of operatively associated ball screw assemblies that enable movement of the top frame with respect to a bottom frame of the leveler. The bottom frame has at least a second set of rolls mounted thereon. The leveler may further include at least one motor operatively associated with the plurality of ball screw assemblies. The motor is designed to drive the plurality of ball screw assemblies to move the top frame. The motor may also have at least one operatively associated encoder configured for monitoring or communicating data associated with rotation of the ball screw assemblies. The leveler may also include at least one position transmitter configured for monitoring a position of at least a portion of the top frame relative to a position of at least a portion of the bottom frame.
Abstract: Apparatus for housing electrically powered components to protect such components from damage and interference caused by lightning strikes and other externally generated magnetic fields. On embodiment includes a shielded enclosure mounted on an electrically groundable platform mounted on legs. An extendable and retractable mast is disclosed and may be supported on the platform and electrically grounded thereto. In another embodiment, the platform is portable and the shielded enclosures may be mounted to the electrically groundable platform by shock absorbers and be electrically grounded thereto. Adjustable outriggers may also be mounted to the platform.