Abstract: Bias controllers are provided which alter a bias control signal so that a bias signal (e.g., a current signal) of an electronic network rapidly responds to increases in the rate-of-change of the network's analog input signal. This enhances the linearity of a system that includes the electronic network. Subsequent decreases in the rate-of-change are sensed and a decrease of the bias control signal is then paced at a rate selected to ignore short-term rate-of-change variations (e.g., modulation variations) but follow longer-term rate-of-change reductions to thereby enhance system efficiency without sacrificing system linearity.

Abstract: A voltage regulator includes a linear mode regulator having a high pass filter circuit connected between its output and an output node, and a switch mode regulator having an low pass filter circuit connected between its output and the same output node. The high pass filter passes high frequency AC current provided by the linear mode regulator to the output node and reduces the low frequency AC and DC currents to substantially zero, and the low pass filter prevents the high frequency AC current produced by the linear mode regulator from being drawn by the switch mode regulator and passes the low AC and DC currents provided by the switch mode regulator to the output node. Thus, the present regulator offers the high response speed and low noise of a linear mode regulator, and the high power efficiency and large continuous output current capability of a switch mode regulator.

Abstract: Timing enhancements of embodiments of the invention are realized in time-interleaved converter systems with minimal network additions that facilitate the insertion of a timing signal into the system's input analog signal. The timing signal travels with the input analog signal so that it continues to accurately define predetermined sample times in the analog signal even as they travel over different path lengths to individual converters. Each converter has a feedback path which adjusts the timing of that converter's samples with a correction signal whose value is determined by contributions of first and second different amplitudes of the timing signal to that converter's output signals.

Abstract: Efficient re-computation of an error detection code is achieved with an original data message that includes a payload and an error detection code. The error detection code comprises a value determined according to an error detection formula using the payload. The payload is modified using a payload transformation formula. The error detection code is re-computed from the original error detection code, rather than from the modified payload. The formula for re-computing the error detection code is different from the formula used to originally obtain the error detection formula, and does not use the original payload or the modified payload.

Abstract: A MEMS module is provided comprising at least one MEMS device adhesively bonded to a substrate or wafer, such as a CMOS die, carrying pre-processed electronic circuitry. The at least one MEMS device, which may comprise a sensor or an actuator, may thus be integrated with related control, readout/signal conditioning, and/or signal processing circuitry. An example of a method pursuant to the invention comprises the adhesive bonding of a pre-processed electronics substrate or wafer to a layered structure preferably in the form of a silicon-on-insulator (SOI) substrate. The SOI is then bulk micromachined to selectively remove portions thereof to define the MEMS device. Prior to release of the MEMS device, the device and the associated electronic circuitry are electrically interconnected, for example, by wire bonds or metallized vias.

Abstract: An output buffer for driving a capacitively-terminated transmission line produces a waveform which comprises a first portion during which the waveform transitions from a voltage V1 to a voltage V2; a second portion during which it remains fixed at V2; a third portion during which it transitions to a voltage V3; and a fourth portion during which it remains fixed at V3. The waveform is created within a unit interval whenever successive data bits transition between logic states. The first and second portions are generated with circuitry arranged such that V2 is maximized by reducing the buffer's output impedance. The fourth portion is generated with circuitry which has a non-zero output impedance preferably equal to the transmission line's characteristic impedance, to absorb transitions reflected back to the source circuitry by the capacitive termination.

Abstract: A method and apparatus for forming a porous layer on the surface of a semiconductor material wherein an electrolyte is provided and is placed in contact with one or more surfaces of a layer of semiconductor material. The electrolyte is heated and a bias is introduced across said electrolyte and the semiconductor material causing a current to flow between the electrolyte and the semiconductor material. The current forms a porous layer on the one or more surfaces of the semiconductor material in contact with the electrolyte. The semiconductor material with its porous layer can serve as a substrate for a light emitter. A semiconductor emission region can be formed on the substrate. The emission region is capable of emitting light omnidirectionally in response to a bias, with the porous layer enhancing extraction of the emitting region light passing through the substrate.

Abstract: Comparator systems are provided that include first and second differential pairs of transistors with inherent offsets that are a function of their tail currents. Some system embodiments configure the pairs to have substantially-equal, nonzero inherent offset voltages and other embodiments configure them to have substantially-zero inherent offset voltages. The systems further include a feedback network arranged to provide a second tail current to the second differential pair that substantially nulls the second output signal of this differential pair when it is driven by a reference signal. The feedback network generates an identical first tail current for the first differential pair which will now accurately compare an input signal to the reference signal.

Abstract: An elongated perimeter light is disclosed, which comprises a linear array of light sources (LEDs) that are electrically illuminated. The array of light sources is disposed within an elongated transparent tube, with the tube transmitting and dispersing the light from the array giving the appearance that said array of light sources is a continuous light source. The array of light sources is capable of being cut at intervals down its length to shorten it. The light sources that remain in the array continue to emit light and the tube can be cut to match the length of said array. The present invention also discloses systems for lighting structural features, with one system according to the present invention comprising a plurality of elongated perimeter lights. The perimeter lights are electrically coupled in a daisy chain with the electrical power at each of the perimeter lights being transmitted to the successive light.

Abstract: A dispenser for a solid, gel or paste product includes a sound generating component or transmitter which releases a preset audio message, or which can activate other devices, every time the product is delivered from the dispenser.

Abstract: The present invention is directed to an improved system and method in which a pen-sized and shaped device detects, recognizes and stores handwriting as it is written by the device. The invention employs both an active feedback network and a character recognition methodology of partitioning detected input into character components. The active feedback network continually monitors device output to determine the sufficiency of the data input. If the data input is insufficient, the device modifies its detection methodology to obtain data the device readily recognizes. Data recognition is performed in multiple asynchronous processes. Elements of individual characters are sampled by the detector. Character elements are processed and recognized on this elemental level. Recognized character elements are stored for subsequent assembly and recognition on a character level. Thus, preferably two recognition sub-processes take place, one on a character element level and another on a character level.

Abstract: A retracting tether apparatus is disclosed comprising a retractor housing having a locking post on its outside surface. The apparatus also includes an attachment mechanism, such as a belt clip, for attaching to a body and a retaining section, the attachment mechanism being integral to the retaining section. The retaining section has a retaining section hole sized to mate with the locking post and the locking post has a mechanism for holding the post in the retaining section hole. The inside surface of the retaining section hole rides on an outside surface of the locking post to provide for smooth rotation of the retractor housing in relation to the retaining section.

Abstract: A bipolar differential input stage with an input bias current cancellation circuit comprises an input pair and a bipolar tracking transistor. The input stage is arranged such that the collector currents in the input pair and tracking transistor, and the collector-emitter voltages of the input pair and tracking transistor, are substantially equal. A lateral PNP transistor's first collector provides the tracking transistor base current required to achieve the substantially equal collector current, and second and third collectors provide copies of the tracking transistor base current as bias current cancellation currents to the bases of the input pair, thereby reducing the input stages' input bias currents.

Abstract: A semiconductor switch includes a thyristor and a current shunt, preferably a transistor in parallel with and controlled by the thyristor, which shunts thyristor current at turn-off. The thyristor includes a portion of a drift layer, with a p-n junction formed below a gate adjacent to the drift layer to establish a depletion region with a high potential barrier to thyristor current flow at turn-off. The drift layer also provides the transistor base, as well as a current path allowing the transistor base current to be controlled by the thyristor. The switch is voltage controlled using an insulated gate.

Abstract: A common mode linearized input stage comprises NPN and PNP differential pairs biased with respective tail currents at respective common emitter nodes, with each pair connected to receive a differential input signal. A tail current modulation circuit generates complementary output currents as a function of the voltage difference between the common emitter nodes, and first and second tail current sources generate the tail currents as a function of the complementary output currents. The tail current modulation circuit and the first and second tail current sources are arranged such that the magnitudes of the tail currents increase with an increasing differential input signal.

Abstract: A current integration circuit includes an operational amplifier having a capacitor connected between its output and inverting input which integrates an input current. To prevent the op amp's output from becoming saturated, a charge dumping circuit dumps a known charge of the opposite polarity to that stored on the capacitor to the op amp's inverting input, thus reducing the charge on the capacitor and preventing the op amp's output from becoming saturated. A charge dump is triggered whenever the op amp's output exceeds a predetermined trip voltage. Counting the number of charge dumps performed during a given integration period provides a coarse indication of the magnitude of the integrated input current, and the output of the op amp provides a fine indication.

Abstract: A digital blanking circuit allows a first digital input signal transition to be passed on to a following stage, but prohibits the passing of subsequent transitions for a predetermined blanking interval. One embodiment of the present invention employs rising edge and falling edge latches, the inputs of which receive the digital input signal and the outputs of which are connected to a two-to-one multiplexer. The mux output is connected to a blanking interval circuit, which is triggered to begin timing a blanking interval by a multiplexer output transition. The blanking interval circuit provides outputs which control the latches and selects the latch output to be transferred to the multiplexer output such that the multiplexer output is prevented from transitioning during a blanking interval.

Abstract: Computer-implemented techniques are provided for synthesizing sounds of an internal combustion engine vehicle using a physical model of the vehicle. In general terms, the method includes independently generating and/or synthesizing separate components of the vehicle sound, then combining these components to produce a final sound. Using a physical model of the vehicle, the separate components of the vehicle sound are independently generated from vehicle control parameters characterizing the operating conditions of the vehicle. The components are then combined using mixers and equalizers to produce a realistic vehicle sound. The present technique allows independent control of the separate components of the vehicle sound, is not limited to specific vehicles, and does not require recorded sounds taking large amounts of storage space.

Abstract: A switched noise filter circuit for DC-DC converters which use the instantaneous output voltage to establish the converter's duty ratio. The converter cycles the switching element on and off for time intervals Ton and Toff, respectively. A switching control circuit includes a filter capacitance connected between the feedback node and ground, and a comparator which compares a feedback voltage Vfb with a fixed voltage Vref; at least one of Ton and Toff is a “modulated” interval which is terminated when Vfb crosses Vref due to the discharge of the filter capacitance. A switched noise filter circuit applies an offset voltage to Vfb during at least one of Ton, and Toff, with the offset voltage disconnected from Vfb by the beginning of the modulated interval or shortly thereafter. When the offset voltage is properly applied, the effect of extraneous electromagnetic noise coupled into Vfb is reduced.

Abstract: Test probe pads are located lateral to, and spaced from, the emitter, base or collector region of a bipolar transistor, preferably on separate pedestals, and connected to their respective transistor regions by air bridges. The probe pads, transistor contacts and air bridges are preferably formed as common metallizations. In the case of an HBT, a gap in the subcollector below the air bridges insulates the test transistor from capacitor loading by the probe pads. The test transistors can be used to characterize both themselves and functional circuit transistors fabricated with the same process on the same wafer by testing at an intermediate stage of manufacture, thus allowing wafers to be discarded without completing the manufacture if their transistors do not meet specifications.