Abstract: Apparatus and method for measurement of the activity of a central processing unit of a data processing system resulting from the execution of a program or series of programs. A value is initially entered in an arithmetic circuit. Each time an instruction is executed, a quantity related to the amount of activity required to execute the instruction is decremented from the arithmetic circuit. When value in the arithmetic circuit reaches zero, the operating system is notified and a decision whether to continue the program or initiate some other activity in the data processing unit is made. The usage of the machine is therefore determined by the number of times the arithmetic circuit has reached zero during the execution of a program and by the quantity remaining in the arithmetic circuit when execution of the program is complete. Provision is made for other measurement modes such as decrementing the quantity in the arithmetic circuit by a clock.

Abstract: Apparatus for entering encoded data, command, and address information via a keyboard for transfer to an automated maintenance system designed to perform certain tests on or cause selected events in a unit of a data processing system such as the central processing unit. The data, command and address information entered via the keyboard by an operator serves to control the tests performed by or the events caused by the automated maintenance system. The maintenance panel also includes a plurality of display devices for displaying the data, command and address information sent to the automated maintenance system as well as data received by the automated maintenance system from the unit under test indicating the correctness of its performance. In the preferred embodiment, several LED indicators are also used for prompting and status indication.

Abstract: An apparatus for conducting input output operations with another data processing device in a flexible and low cost manner is comprised of a programmed microprocessor coupled to a keyboard, a parallel port, and a modem. The microprocessor is programmed to periodically scan the keyboard to determine what keys if any are depressed. It also scans the parallel port for incoming data and senses incoming data from the modem by sensing a start bit. Control characters from the keyboard can set options such that incoming data from an input can be simultaneously sent out from the modem and/or parallel port.

Abstract: Two switching elements are cross-coupled in the standard bistable multivibrator arrangement. Two additional switching elements are added: one each in parallel with one of the switching elements forming the bistable multivibrator. The two wave forms under study are applied to the control gate of each of the additional switching elements. When both wave forms are in one state, the two additional switching elements are switched ON, effectively inhibiting bistable multivibrator action. The first wave form to change state results in its associated switching element switching OFF, which releases the bistable multivibrator circuit to assume the corresponding stable state, which observed differentially across the switching element forming the bistable multivibrator, is indicative of the wave form to first undergo transition.

Abstract: A slowly varying bias signal is added to one input of a Wave Form Transition Sequence Detector, as more fully described in a related application cited herein, to provide a differential output therefrom which is directly proportional to the time between transitions occurring on two input wave forms. The slowly varying bias modulates the level of one input wave form, and thereby varies the time required for the Wave Form Transition Detector to detect a transition occuring thereon. By symmetrically varying the response time of the Wave Form Transition Sequence Detector to one input wave form in the neighborhood of the occurrence of a transition on the second input waveform, the average differential output of the Wave Form Transition Sequence Detector over a cycle of the slowly varying bias level will be proportional to the time between transitions occurring on the two input wave forms.

Abstract: A battery charging circuit includes a switching transistor which controls the flow of charging current to the battery at a high rate or a low rate. The operation of the transistor is, in turn, controlled by a voltage sensing circuit which includes a voltage detector module characterized in a very low current drain. The battery is, in fact, isolated from the charging circuit by a diode; the sensing circuit, however, is not isolated from the battery by a diode. This arrangement permits a more sensitive voltage detection and a more accurate control over the switching transistor. A desirable switching hysteresis is built into the sensing circuit but is operable to allow the hysteresis loop to be eliminated for purposes of calibration.

Abstract: A computer based process control system includes a digital event counter input circuit wherein a number of data sources are scanned. A sensed status of the individual input point is compared with the previous status of that point to determine if a change of status has occurred, indicative of an event to be counted. The previous status is stored in a dedicated register. If the comparison indicates that a countable event has occurred, a counter is incremented; also the dedicated register is updated to indicate the present status of the scanned point. The counter status is stored in an accompanying memory which may then be read out by an external device such as a processor.

Abstract: A digital input circuit is provided wherein previous digital data is stored in a holding register. Subsequent data is compared with the data in the holding register to determine whether or not a change had occurred in the input data from the primary sensors. If no change is detected, the system effectively "passes" on that scan of the data. If, on the other hand, a change has been detected an interrupt signal is generated for transmission back to the host computer. The host computer may then initiate a "read" sequence. The "read" sequence under ordinary circumstances, includes updating the data in the storage register before enabling the outputting of the digital data.

Abstract: A computer system features a processor unit which includes its own microprogram control unit. The microprogram control unit includes a storage means for operational instructions for the processor unit and means to issue those instructions in a desired sequence. A communication Bus provides communication channels between the processor unit and either data storage means or other processor units served by the Bus. The processor unit includes a number of clock controlled functional components as well as means for requesting access to the Bus. A clock signal generating means is controlled by signals from the microprogram control unit. When a request has been made for access to the Bus, the processor continues to operate until a point is reached when access to the Bus must be accomplished before continuing. The microprogram control unit issues a control signal which effectively stops the operation of the clock signal generating means until the Bus access routine has been accomplished.

Abstract: A latensifier for developing latent images recorded on direct print paper includes a pair of generally U-shaped fluorescent lamps mounted to expose the paper to latensifying radiations, the planes of said lamps being disposed at a right angle to each other, with a neutral density step filter arranged in association with one of the lamps to control pre-conditioning radiation to the paper, reflectors operatively associated with the second of the lamps to control additional pre-conditioning radiation to the paper and also to allow maximum use of the second lamp for recorded image development, the second lamp being selectively energized in accordance with the speed of relative movement of the lamps and paper.

Abstract: A magnetic recording head driving circuit includes a single operational differential amplifier which mixes the bias signals with the data signals, the signal level of the two signals being separately controlled. The output of the amplifier is applied to the recording head through an impedance matching network. The impedance matching network converts the relatively high inductive impedance of the head to a substantially and effectively resistive load, matching the output impedance of the amplifier at the frequency of the bias signal.

Abstract: A self retaining read-out block has a pair of flexible legs that form separate integral spaced apart rear side surfaces of the block. The flexible nature of these legs allow each leg to be readily placed in a bowed position so that each free end can be snapped into captive engagement with a different one of two stops that are located on each of the inner side walls of the module chassis. The spring force generated in each leg while it is bent into a bowed position is used to force the read-out block and a front panel card associated therewith away from each of their associated stops and into spring loaded mounted engagement against an edge of the module chassis that forms a front opening therein.