Abstract: A clock security ring provides improved clock system error detection and (a.c.) fault isolation. The clock security ring is formed by a plurality of fault detection circuits and a plurality of error collection circuits each receiving inputs from respective subsets of the plurality of fault detection circuits. The error collection circuits comprise a logical network which provides a detected fault output for any fault pattern which leaves at least one fault detection circuit in a predefined correct state. Each of the subsets of fault detection circuits has an arbitrary grouping of fault detection circuits plus one fault detection circuit from an adjacent subset to thereby form a ring structure. The outputs of the error collection circuits are analyzed to provide fault isolation.