Abstract: A process for defining improved tapered contact openings in glass coatings comprising the deposition of a layer of low temperature flowable passivating glass and the deposition of a masking layer to initially approximately define contact areas over portions of the active regions and over portions of a gate line. The first contact openings are then etched and the passivating layer caused to reflow followed by a second etch, in the previously etched areas, which second etch accurately defines the contact openings. The final etch rounds off any corners produced by the second etch to produce smoothly tapered contact openings. .circle.

Abstract: The basewidth of a lateral, bipolar transistor is markedly reduced by first forming a layer of polycrystalline silicon over an oxide coated substrate. By utilizing a process for doping the exposed edges of the patterned polysilicon layer, a narrower basewidth dimension is achieved than heretofore possible with photolithographic techniques.

Abstract: A silicon-on-sapphire structure and method for forming the same is described wherein the leakage current attributable to "back channel" leakage is minimized by forming the channel region in such a manner as to have provided therein at least two levels of dopant concentration. The heavier level of dopant concentration is positioned adjacent the silicon/sapphire interface while the lighter level of dopant concentration occupies the remainder of the channel region and is shallower than the heavier level. The classic inversion process takes place in the lightly doped section at the shallow level.

Abstract: A method of making a monolithic semiconductor-on-insulator device which includes silicon islands in spaced relation on the surface of an insulating substrate includes the steps of filling the spaces between the islands with a passivating material by first depositing a layer of a semi-insulating material on the surface of the substrate and extending between adjacent islands into contiguous relation with the side surfaces thereof and then depositing a layer of insulating material on the layer of semi-insulating material. The combined thicknesses of the layers of semi-insulating and insulating material is substantially the same as the thickness of the silicon islands so that the resulting device has a substantially planar surface.

Abstract: An MNOS device is described wherein a body of semiconductor material is provided with source and drain regions and an interstitial portion, representing the channel region, therebetween. The channel region has an area, precisely aligned with the gate, that has been implanted with additional conductivity modifiers of the same conductivity type as the remaining portions of the channel region.

Abstract: A semiconductor wafer is cleansed of loose foreign surface matter and chemical impurities near the surface in an apparatus which passes superheated steam over the wafer. Condensate is permitted to form and drip off the wafer. After rising above 100.degree. C. the wafer becomes dry, and is removed from the apparatus and then permitted to cool.

Abstract: A field-effect device with closed floating gate geometry suitable for use as a storage element in a non-volatile memory array.

Abstract: An improved process of forming planar silicon-on-sapphire MOS integrated circuit devices by a local oxidation process in which portions of a silicon layer on a sapphire substrate are thermally oxidized throughout the thickness of the layer to provide interdevice dielectric isolation and a substantially planar topology includes a step of ion implanting phosphorus, boron, or a combination thereof into the silicon prior to the thermal oxidation step. The implanted impurities have a stabilizing effect on the devices thereafter built in the remaining silicon.

Abstract: A complementary MOS inverter includes transistors each of which has a dual gate structure with the threshold voltage of the channel nearest the drain of each transistor arranged to be lower than that of the channel nearest the source of each transistor. This arrangement provides the cascode characteristics of dual gate structure, i.e., high breakdown voltage, high voltage gain, low drain output conductance, and relatively fast frequency response, but allows all four gate electrodes of the transistors to be connected in common, thus enabling relatively simple layout.

Abstract: A floating gate semiconductor device is described wherein the floating gate member does not extend completely across the channel region and thus avoids alignment with the edges of the source and drain regions. The lateral displacement of the edge of the floating gate from the drain region permits stored charge on the drain to be undisturbed in the event avalanche breakdown occurs at the channel-drain junction.

Abstract: A semiconductor device includes a region of polycrystalline silicon on a portion of the surface of a body of semiconductor material. A layer of oxidized polycrystalline silicon is also on the semiconductor material body and extends to the polycrystalline silicon region. The surface of the silicon oxide layer is substantially coplanar with the surface of the polycrystalline silicon region so that a metal film conductor can be easily provided over the semiconductor device. The polycrystalline silicon region may be the gate of an MOS transistor or a conductive region of any type of semiconductor device. The semiconductor device is made by forming a polycrystalline silicon layer over the semiconductor material body, forming a mask on a portion of the polycrystalline silicon layer, reducing the thickness of the unmasked portion of the polycrystalline silicon layer and then oxidizing the unmasked portion of the polycrystalline silicon layer to form the oxide layer.

Abstract: A signal sampling circuit is disclosed which accommodates itself to operation during the presence of high noise levels encountered, for example, when attempting to monitor and control, and thus optimize, the functioning of an internal combustion engine. Noise detection means is provided for detecting the presence or absence of noise pulses during either a request for a signal sample or during a signal sampling period. When the noise detector indicates the presence of noise during the request or during the sampling period, the derived information is disregarded and either reread during the next, noise-free period or is resampled shortly after the sampling interval in which the discarded information was obtained.

Abstract: A semi-planar silicon-on-sapphire composite comprises a sapphire substrate, an epitaxial monocrystalline silicon mesa formed adjacent the substrate and an epitaxial deposition of monocrystalline aluminum oxide surrounding the mesa.

Abstract: A dual time constant, phase lock loop indicator is described which will respond in one manner to signals indicating an "unlocked" condition and respond in another, different manner to signals indicating a "locked" condition.

Abstract: A multiplex addressing system for use with a multi-element array of liquid crystal electro-optic devices wherein all elements of a selected row are turned on by applying a predetermined activating voltage to all the elements of the row, then erasing the selected and non-selected elements in the row by a lesser and a greater amount to effect predetermined on and off responses, to take advantage of the highly non-linear erase response of the electro-optic devices.

Abstract: A method of making an improved aluminum oxide (sapphire) gate field effect transistor wherein the capacitance-voltage characteristic of the transistor is improved by annealing the aluminum oxide at a temperature less than the growth temperature of the aluminum oxide. A transistor annealed at a temperature less than the growth temperature is provided wherein the threshold voltage is the same as if the transistor were annealed at a temperature greater than the growth temperature; the capacitance-voltage characteristic of the transistor exhibiting markedly diminished hysteresis by annealing at a temperature less than the growth temperature.

Abstract: A composition of matter produced by a process wherein silicon is bombarded by phosphorus ions and phosphorus ions are implanted therein. A method for rendering silicon substantially unetchable in a potassium hydroxide etchant by implanting phosphorus in the silicon by brombardment with phosphorus ions.