Patents Represented by Attorney Laleh Jalali
  • Patent number: 8129749
    Abstract: Double quantum well structures for transistors are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a first quantum well channel coupled with the first barrier layer wherein the first quantum well channel includes a group III-V semiconductor material or a group II-VI semiconductor material, or combinations thereof, a second barrier layer coupled to the first quantum well channel, and a second quantum well channel coupled to the barrier layer wherein the second quantum well channel includes a group III-V semiconductor material or a group II-VI semiconductor material, or combinations thereof.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: March 6, 2012
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Mantu K. Hudait, Marko Radosavljevic, Gilbert Dewey, Titash Rakshit, Jack T. Kavalieros
  • Patent number: 8101471
    Abstract: A programmable anti-fuse element includes a substrate (224), an N-well (426) in the substrate, an electrically insulating layer (427) over the N-well, and a gate electrode (430) over the electrically insulating layer. The gate electrode has n-type doping so that the N-well is able to substantially contain within its boundaries a current generated following a programming event of the programmable anti-fuse element. In the same or another embodiment, a twice-programmable fuse element (100) includes a metal gate fuse (110) and an oxide anti-fuse (120) such as the programmable anti-fuse element just described.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: January 24, 2012
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan, Jie-Feng Lin, Chetan Prasad, Sangwoo Pae, Zhanping Chen, Anisur Rahman
  • Patent number: 7995068
    Abstract: A method, apparatus, and signal-bearing medium for sending to a display device only those regions of the display screen that change. A frame buffer is divided into tiles, which may be composed of one or more regions, and data in the frame buffer represents pixels on the display screen. When data representing a pixel is modified in the frame buffer, the region or tile associated with the pixel is marked as dirty, and those tiles or regions that are dirty in the frame buffer are written to the display.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: August 9, 2011
    Inventors: Thomas E. Willis, Steven L. Midford
  • Patent number: 7889951
    Abstract: In an embodiment, an apparatus includes a first processor that includes a first processor element. The apparatus also includes a second processor that includes a second processor element. The first processor is configured to transmit data to the second processor through a third processor, wherein no processor element within the third processor is configured to perform a process operation on the data as part of the transmission of the data from the first processor to the second processor.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: February 15, 2011
    Assignee: Intel Corporation
    Inventor: Louis A. Lippincott
  • Patent number: 7842537
    Abstract: A stressed semiconductor using carbon is provided. At least one carbon layer containing diamond is formed either below a semiconductor layer or above a semiconductor device. The carbon layer induces stress in the semiconductor layer, thereby increasing carrier mobility in the device channel region. The carbon layer may be selectively formed or patterned to localize the induced stress.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Kramadhati V. Ravi, Brian S. Doyle
  • Patent number: 7821044
    Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: October 26, 2010
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Steven J. Keating, Thomas A. Letson, Anand S. Murthy, Donald W. O'Neill, Willy Rachmady
  • Patent number: 7812455
    Abstract: A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate; etching the first insulator layer at a selected location to provide at least a first via to the semiconductor substrate; depositing the first metal on the semiconductor substrate to form at least a first metal contact plug in the first via in contact with the semiconductor substrate; treating the semiconductor substrate with an in-situ plasma of a nitrogen containing gas wherein the plasma forms a nitride layer of the first metal at least capping a top surface of the first metal plug in the first via; and forming a second metal contact to the metal nitride layer capping at least the top surface of the first metal plug.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: October 12, 2010
    Assignee: Intel Corporation
    Inventors: Sean King, Ruth Brain
  • Patent number: 7364943
    Abstract: A method and an arrangement to bond a die to a substrate of a die-substrate combination to form a microelectronic package. The method comprises: providing the die-substrate combination including a die, a substrate, pre-connection bumps and an underfill material, the pre-connection bumps and underfill material being disposed between the die and the substrate; forming joints from the pre-connection bumps at a joint formation site to obtain an intermediate package; curing the underfill material of the intermediate package at an underfill curing site to obtain the microelectronic package; using a conveying device to transfer the intermediate package from the joint formation site to the underfill curing site; and applying heat energy to the intermediate package during at least part of a transfer thereof from the joint formation site to the underfill curing site to control a temperature of the intermediate package.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: April 29, 2008
    Assignee: Intel Corporation
    Inventors: James P. Mellody, Sabina J. Houle
  • Patent number: 7339276
    Abstract: Placing a flow modifier on a package substrate to create two flow fronts on a molded matrix array package. A flow modifier may be laid on a package substrate to a height that blocks off the bottom of other substrates (e.g., dice) coupled to the package substrate. By separating the top flow front and the bottom flow front, this process prevents the top flow front from wrapping around the sides of the substrates and trapping air below each substrate and in front of the bottom flow front.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: March 4, 2008
    Assignee: Intel Corporation
    Inventors: Rahul N. Manepalli, Saravanan Krishnan, Choong Kooi Chee
  • Patent number: 7317257
    Abstract: A method and apparatus for inhibiting the flow of a flowable adhesive material disposed adjacent to a substrate. A chip component is disposed adjacent to a substrate and a plurality of nanoparticles are disposed and cured adjacent to the substrate and proximate to the chip component. The nanoparticles possess surface properties that make them substantially immiscible with a flowable adhesive. The band of nanoparticles will inhibit the flow of a flowable adhesive material disposed between the chip and the nanoparticles, in a direction bounded by the plurality of nanoparticles, while adhesive flow in the direction of the component is promoted.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: January 8, 2008
    Assignee: Intel Corporation
    Inventors: Chun Hwa See, Szu Shing Lim
  • Patent number: 7279720
    Abstract: The invention provides bumps between a die and a substrate with a height greater than or equal to a height of a waveguide between the die and the substrate. The bumps may be formed on a die prior to that die being singulated from a wafer.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: October 9, 2007
    Assignee: Intel Corporation
    Inventors: Ming Fang, Valery Dubin, Daoqiang Lu
  • Patent number: 7268077
    Abstract: A method and apparatus including an interconnect structure having a surface, a plurality of nanotubes disposed adjacent to the surface, and a metallic layer disposed adjacent to the surface and substantially including the nanotubes. An assembly may include a first embodiment of an apparatus as described, and may further include a second such embodiment at least one of physically and electrically coupled to the first embodiment.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: September 11, 2007
    Assignee: Intel Corporation
    Inventor: Chi-Won Hwang
  • Patent number: 7237334
    Abstract: A method of providing a printed circuit board, a printed circuit board formed according to the method, and a system comprising the printed circuit board. The method comprises: providing a microelectronic substrate; providing a via-defining substrate by providing via openings in the substrate using laser irradiation; providing a laser activatable film on the via-defining substrate; and providing interconnects on the via-defining substrate. Providing interconnects comprises providing a patterned build-up layer on the via-defining substrate comprising exposing the laser activatable film to laser irradiation to selectively activate portions of the film according to a predetermined interconnect pattern; and metallizing the patterned build-up layer according to the predetermined interconnect pattern to yield the interconnects to provide the printed circuit board.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: July 3, 2007
    Assignee: Intel Corporation
    Inventor: Islam A. Salama
  • Patent number: 7235870
    Abstract: A method of fabricating a microelectronic multi-chip module comprises: providing a cavity down ball grid array having a die and solder balls on a die side thereof; providing a package including at least one die thereon on a die side thereof; stacking the package onto the backside of the ball grid array opposite from the die side of the ball grid array. The backsides of the ball grid array and of the package may include land pads for providing interconnection between the ball grid array and the package during stacking.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: June 26, 2007
    Inventors: Nelson V. Punzalan, Jr., Marcelino Ian W. Estinozo, II
  • Patent number: 7224067
    Abstract: Embodiments of the invention provide a low-melting temperature comprised primarily of a bulk intermetallic phase material. This solder may allow reflow with less of a chance to damage microelectronic devices due to coefficient of thermal expansion mismatches, and may be creep resistant even at high homologous temperatures.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: May 29, 2007
    Assignee: Intel Corporation
    Inventor: Daewoong Suh
  • Patent number: 7220624
    Abstract: An apparatus and method for releasing pressure existing within a package comprising a substrate to which a die is attached to provide electrical connections between the die and the exterior of the package, a lid, and sealant disposed between the substrate and the lid in a pattern with at least one break in the pattern.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventors: Sudipto Neogi, Biswajit Sur, Boon Seng Tan, Chris Rumer
  • Patent number: 7190078
    Abstract: A method of forming an interconnection structure in a microelectronic package, and an interconnection structure of a microelectronic package formed according to the method. The method includes: providing a combination including a first conductive layer and a dielectric layer fixed to the conductive layer; providing a hole through the dielectric layer extending from a surface of the dielectric layer to the first conductive layer; providing a recess in the first conductive layer and in communication with the hole to provide an interlocking volume under the dielectric layer; providing a conductive material in the hole and in the recess to form a package via having an interlocking section in the interlocking volume of the recess; and providing a conductive material on the dielectric layer to form a second conductive layer adapted to be in electrical contact with the first conductive layer through the package via.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: March 13, 2007
    Inventors: Viren V. Khandekar, Jesus L. Munoz, Lilia Benigra-Unite, Mario M. Tobias
  • Patent number: 7183162
    Abstract: A method of forming a microelectronic non-volatile memory cell, a memory cell formed according to the method, and a system including the memory cell.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: Steven R. Soss, Krishna Parat
  • Patent number: 7166505
    Abstract: A method for making a semiconductor device is described. That method includes forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: January 23, 2007
    Assignee: Intel Corporation
    Inventors: Robert Chau, Reza Arghavani, Mark Doczy
  • Patent number: 7011726
    Abstract: A method of fabricating a thin dielectric film, a thin dielectric film formed according to the method, and a system including the thin dielectric film. The method includes: depositing a ceramic precursor material on a metal sheet, the ceramic precursor material including a mixture comprising ceramic particles and an organic carrier medium; heat treating the ceramic precursor material such that the organic carrier medium is substantially burnt off, and further such that a dielectric layer is formed including ceramic grains formed from the ceramic particles, and having grain sizes between about 100 nm and about 500 nm; depositing a CSD precursor material onto the dielectric layer; and heat treating the CSD precursor material such that organics in the CSD precursor material are substantially burnt off, and further such that a CSD medium is formed from the CSD precursor material including CSD grains substantially filling the voids between the ceramic grains.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: March 14, 2006
    Assignee: Intel Corporation
    Inventor: Cengiz A. Palanduz