Abstract: A router for funneling a plurality of conductors is disclosed. The router includes a routing unit and a plurality of conductor paths. The conductor paths are directed through the routing unit and are adapted to receive the conductors. The routing unit and the plurality of conductor paths are formed by a three-dimensional fabrication process.

Abstract: A tester that is well suited for operation at high speeds or with narrow pulses. The tester includes a state based pulse shaping circuit that combines edge signals into a pulsed output signal. The circuit combines groups of set and reset signals. The edge signals define the start and stop of pulses in the output signal even if the set and reset edge signals overlap or successive set signals overlap or successive reset signals overlap. This circuit allows for a low cost and low power CMOS implementation of an output signal formatter.

Abstract: A contact housing adapted for carrying a plurality of compliant contacts is described. The contact housing is for use in contacting a semiconductor wafer-level package having an array of contacts disposed in a predetermined pattern. The contact housing includes a first guide plate formed from a material having a temperature coefficient of expansion approximating that of the semiconductor wafer-level package. The guide plate has a first pattern of apertures formed by a microelectromechanical process such that the pattern of apertures matches the predetermined pattern of contacts on the wafer-level package. A second guide plate is formed similar to the first guide plate, and includes a second pattern of apertures disposed in vertical registration with the first pattern of apertures. A spacer is interposed between the first and second guide plates. The first and second guide plates cooperate with the spacer to form respective receptacles adapted for carrying the plurality of compliant contacts.

Abstract: An automatic test system for testing smart card chips. The system includes synchronization circuitry that allows response signals generated at random times after a stimulus to be synchronized with a pattern generator. The described system has multiple paths in the synchronization circuitry that allows responses from several devices under test to be synchronized with each other so that parallel testing is supported. The system is well adapted for testing of smart card chips because such chips often respond to stimulus at random times. Other adaptations are included for testing of smart card chips. These adaptations include circuitry to generate a modulated RF carrier signal and signal processing circuitry that can detect modulation imposed on the RF carrier, allowing the smart card chip to be tested without modifications to the device for test access.

Abstract: A modular power supply architecture for automatic test equipment is disclosed. The power supply architecture includes a control module having a control signal output line and a plurality of output modules. The control module includes control circuitry to generate a control signal along the control signal output line and measurement circuitry coupled to the control signal output line. The output modules have respective control inputs coupled in parallel to the control signal output line to receive the control signal and respective current outputs connected in parallel. The output modules are operative in response to the control signal to generate respective currents at the current outputs. A current output bus receives and sums the respective current outputs, the output bus being isolated from the control signal line.

Abstract: A subassembly to aid in changing the interface unit for an automatic test system. The disclosed embodiment shows an automatic test system with a handler and a tester. The interface unit is a device interface board (DIB). The subassembly allows the DIB to be easily accessed, yet can be properly aligned to the test system. No special tools are required to change the DIB.

Abstract: A strip, leadframe or panel type handling device for use in testing semiconductor components. The handling device has a thermal plate assembly with embedded electrical resistance heaters. The heaters are separately controlled in zones to provide uniform temperature across the plate for elevated temperature testing. Cooling channels are formed in the plate. Intermingling channels are provided to allow different types of cooling fluids to be used to cool at different rates or hold a cold temperature at different levels. The cooling channels can likewise be provided in zones to promote temperature uniformity. Vacuum channels are used to hold the semiconductor parts under test in close contact with the thermal plate.

Abstract: A differential D flip-flop is disclosed including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The data set circuit has a first differential input and a first differential output. The first data store circuit couples to the output of the first data set circuit. The cell further includes a differential clock circuit and a differential reset circuit. The clock circuit having complementary clock inputs to alternately set and store data in the data set and data store circuits. The differential reset circuit ties to the differential output and is operative in response to a reset signal to force the differential output to a predetermined logic level. The differential reset circuit includes matched complementary reset drivers to exhibit like capacitances. The slave cell is formed substantially similar to the master cell, and includes a second differential input coupled to the first differential output of the master cell.

Abstract: An interface module for connecting a plurality of signal paths from a first electronic assembly to a second electronic assembly is disclosed. The interface module includes a plurality of coaxial cables having distal ends adapted for coupling to the first electronic assembly and proximal ends, each cable having a shield conductor and a center conductor. A stiffener formed with a plurality of throughbores receives the proximal ends of the plurality of signal cables, the stiffener having a flat termination side at one end of the plurality of throughbores. The module further includes a signal transition assembly having a flat substrate bonded to the stiffener termination side. The substrate includes respective opposite sides and is formed with spaced-apart signal paths and ground paths extending from one side to the other side.

Abstract: A method tests a subscriber line. The method includes determining values of electrical line features from electrical measurements on the subscriber line and processing a portion of the values of the electrical features with a neural network. The neural network predicts whether the line qualifies to support one or more preselected data services from the portion of the values.

Abstract: The invention is directed to techniques for providing a test procedure for testing a device using automatic test equipment (ATE). An ATE system includes memory having a test application stored therein, a test interface to connect to the device, and a processor coupled to the memory and the test interface. The processor is configured to operate in accordance with the test application to (i) provide a series of instructions based on a test procedure defining a device testing task, and (ii) control the test interface based on the provided series of instructions in order to test the device. The test procedure includes multiple test elements. Each test element defines instructions and programmable input variables that direct the processor to perform a particular test operation of the device testing task. The user of the ATE system combines test elements when creating the test procedure rather than write code from scratch, or modify code of prewritten templates.

Abstract: A high-speed tester channel architecture is disclosed for delivering and receiving signals to and from a device-under-test. The tester channel architecture includes drive/compare circuitry having respective driver and comparator transmission line paths and backmatch resistor circuitry to establish a backmatch condition. Peaking circuitry is disposed in each of the driver and comparator transmission line paths. The peaking circuitry includes a capacitive branch and an inductive branch operative to preserve the backmatch condition.

Abstract: A power supply is disclosed for use with a device-under-test disposed on a device board. The power supply includes a high-accuracy remote supply circuit including respective force and sense lines and a high-speed local supply circuit. The local supply circuit includes an active boost circuit having respective boost and sense lines coupled to the force and sense lines. The active boost circuit is operative to selectively cooperate with the remote supply circuit and, when the device-under-test demands a large dynamic current, provide the dynamic current until the remote supply circuit responds to the current demand.

Abstract: A switching DC-DC converter unit is disclosed that includes an input for receiving a first DC voltage from a DC power source and switching circuitry coupled to the input to generate a switched alternating voltage from the first DC voltage. The switching circuitry includes a plurality of semiconductor switches having respective gate, source and drain leads, and further including noise suppression elements disposed on the drain leads. The unit further includes transformer circuitry coupled to the output of the switching circuitry and conversion circuitry disposed at the output of the transformer circuitry to convert the switched alternating voltage to a second DC voltage.

Abstract: A tester interface assembly is disclosed for coupling a plurality of tester electronic channels to a device-interface-board. The tester interface assembly includes at least one harness assembly having a plurality of coaxial cables, each cable including a body having a center conductor and a shield. The shield is formed coaxially around the center conductor and separated therefrom by a layer of dielectric. Each cable further includes a distal tip formed substantially similar to the body and including respective formed conductive pads disposed on the distal extremities of the center conductor and the shield. The harness employs a housing formed with an internal cavity for receiving and securing the cable distal ends in close-spaced relationship such that the distal tips form an interface engagement plane. A compliant interconnect is interposed between the harness assembly and the device-interface-board, and includes a plurality of conductors formed to engage the cable distal ends along the engagement plane.

Abstract: A differential D flip-flop is disclosed including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The data set circuit has a first differential input and a first differential output. The first data store circuit couples to the output of the first data set circuit. The cell further includes a differential clock circuit and a first current source for generating a fixed bias current in the master cell. The clock circuit having complementary clock inputs to alternatingly set and store data in the data set and data store circuits. The slave cell is formed substantially similar to the master cell, and includes a second differential input coupled to the first differential output of the master cell.

Abstract: A method of determining a redundancy solution for a semiconductor memory under test (DUT) having redundant rows and columns is disclosed. The method includes the steps of first testing the DUT in a first environment with a first tester to generate a first fail data set. The first fail data set is then transferred to a second tester where the DUT is test in a second environment to generate a second fail data set. The first and second failure data sets are then merged to create a merged fail data set. A highly optimized redundancy solution is then determined based on the merged fail data set.

Abstract: A semiconductor parallel tester is disclosed for simultaneously testing a plurality of DUTs secured to a handling apparatus. The test system includes a system controller for initiating system test signals and a pin electronics assembly responsive to the system test signals to generate test pattern signals for application to the plurality of DUTs. The system further includes a signal interface defining a plurality of direct signal paths between the handling apparatus and the pin electronics assembly.

Abstract: Automatic test equipment implemented with low cost CMOS components. Despite the use of CMOS circuitry, which generally has poor timing accuracy, the disclosed test equipment achieves good timing accuracy through the use of several techniques. A delay locked loop is used to compensate for timing variations caused by process variation and slowly varying changes in operating temperature. A frequency dependent heating element is used to avoid temperature induced changes in propagation delays caused by rapid variations in the heat generated by the CMOS circuitry when the operating frequency changes. The design also reduces the number of circuit elements in the critical timing paths which process signals which vary with programmed frequency. To achieve this goal, a continuously running, fixed frequency reference clock is delayed by a fractional amount of one clock period. A counter, also clocked at the reference clock frequency, counts full clock periods.

Abstract: A failure capture circuit for identifying failure location information from a memory-under-test (MUT) having a predetermined storage capacity is disclosed. The failure capture circuit includes failure detection circuitry adapted for coupling to the MUT and operative to apply test signals to the MUT and process output signals therefrom into failure information. The failure information is indicative of failed memory cell locations. A look-up table couples to the failure detection circuitry for storing the location information, thereby minimizing the size of the look-up table and the time to transfer failure data to a redundancy analyzer.