Abstract: Automatic test equipment is disclosed for testing a semiconductor device and including a computer workstation and pin electronics circuitry coupled between the semiconductor device and the computer. The pin electronics circuitry includes a plurality of channels, each channel having timing circuitry operative in response to desired programmed timing information, driver/comparator circuitry coupled to the timing circuitry for driving test waveforms at a period T, and sampling data from the waveforms at a beat period T +/−&Dgr;t, and a timing measurement unit. The timing measurement unit is coupled to the driver/comparator circuitry for measuring the relative timings of the sampled data. The plurality of channels cooperate to produce substantially real-time timing measurement data in parallel.

Abstract: In at least one embodiment, a circuit for a multi-channel tester having a central resource, a plurality of outputs, and a switching matrix coupling the central resource to the plurality of outputs via a plurality of selectable channels. Each of the selectable channels having PIN diodes coupled in a half-bridge configuration. A first, a second, and a third biasing source for forward biasing the PIN diodes. The first and second biasing sources are coupled to a central resource coupled end and an output coupled end of the half-bridge, respectively. The third biasing source is coupled to a common node. The first and second biasing sources are constructed to provide substantially balanced outputs and such that the sum of the outputs of the first and second biasing sources are substantially balanced with respect to the output of the third bias source. In some embodiments, a the plurality of selectable channels comprises the same first biasing source.

Abstract: A timing system is disclosed that responds to pattern generation circuitry for producing test patterns for application to a device-under-test. The timing system includes a timing memory circuit that stores programmed edge timings for the patterns and couples to timing logic including a master oscillator and a plurality of fixed edge generators. The fixed edge generators are responsive to the programmed edge timings to produce the event timing signals.

Abstract: A failure capture circuit for use in a failure processing circuit to identify failure location information from a memory-under-test (MUT) is disclosed. The failure capture circuit includes failure detection circuitry comprising a plurality of channels and adapted for coupling to the MUT. The failure detection circuitry is operative to apply test signals to the MUT and process output signals therefrom into failure information. A failure memory circuit and a high speed link are provided to minimize test time. The high-speed link couples the failure memory circuit to the failure detection circuitry to provide serial data transfer capability therebetween.

Abstract: An automatic test system useful for testing source synchronous devices at high speed. The data outputs of the device under test are routed to channel circuitry within the test system through coaxial cables. The test system includes a buffer amplifier on a device interface board to fan out the DATA CLOCK generated by the device under test to that channel circuitry. The interconnection between the buffer amplifier and the channel circuitry is provided through a coax with low dielectric constant, to compensate for the delay introduced by the buffer amplifier.

Abstract: A high-accuracy linear amplifier is disclosed for sinking or sourcing current to or from a load. The linear amplifier includes input circuitry for receiving a predetermined input signal and rectifier circuitry. The rectifier circuitry is disposed at the output of the input circuitry and is operative in response to the input signal to generate a source/sink command signal. Output stage circuitry is coupled to the rectifier circuitry and includes a current sink transistor and a current source transistor. The output stage circuitry is responsive to the command signal to sink or source current through one of the respective transistors. The amplifier further includes feedback circuitry coupled between the output of the output stage circuitry and the input circuitry to provide an error signal for modifying the input signal. Bias circuitry maintains the non-conducting transistor in an on state during the sourcing or sinking of current.

Abstract: A memory control circuit is disclosed for use in a data path of a failure capture circuit to selectively control the storage of failure information associated with a pin of a device-under-test. The memory control circuit includes a memory controller operative to generate a store signal in response to a failure control signal and a semiconductor memory having a control input coupled to the controller for receiving the store signal. The memory controller operates in response to the store signal to write failure information associated with a particular failure control signal. Disable logic in the memory control circuit is operative according to predetermined conditions for selectively inhibiting the delivery of the failure control signals to the memory controller.

Abstract: A semiconductor memory test system with improved fault data processing and display capabilities. The memory tester includes a lossless data compressor for failure data. Compression allows failure data to be more rapidly transferred to a display device that is part of a work station controlling the memory tester. It also reduces the amount of data that must be stored in the display memory, thereby providing a cost effective way to store data from multiple tests. By allowing data for multiple tests to be stored, the data from a prior test can be used to control the formatting of data for a subsequent test. Such formatting is useful for such things as observing failure mechanisms as the operating temperature or speed of the semiconductor memory under test increases.

Abstract: A driver for applying a deterministic waveform along a lossy transmission path to a device-under-test is disclosed. The driver includes a signal generator for producing a substantially square-wave signal at an output node and an injector coupled to the output node for modifying the square-wave signal to pre-compensate for expected losses along the lossy path.

Abstract: A differential comparator is disclosed including first and second input amplifier circuits. The input amplifier circuits have respective signal input terminals for receiving respective first and second complementary input signals and respective output terminals. The first and second input amplifier circuits cooperate to produce a difference signal. Reference signal circuitry is coupled to the input amplifier circuits and is operative to produce a predetermined reference signal for comparison to the difference signal. The input amplifier circuits and the reference signal circuitry cooperate to define a single stage.

Abstract: A multi-level circuit board for efficiently routing electrical signals is disclosed. The circuit board includes a contact layer comprising a first substrate and formed with a set of contact pads disposed across a relatively large surface area. The contact layer also includes a set of engagement contacts corresponding to the contact pads and arrayed in a densely packed surface area. A plurality of subsequent layers are disposed in fixed stacked relationship to the contact layer. Each subsequent layer includes a subsequent substrate, and a conductive pattern formed on the subsequent substrate and defining a plurality of signal paths. Conductive vias are coupled to the contact pads and the engagement contacts and are formed through the contact layer and one or more of the plurality of subsequent layers. The vias communicate with the respective signal paths and include selected sets of staggered vias configured to optimize the routing of the signal paths along the respective subsequent layers.

Abstract: An analog clock apparatus is disclosed including a digital clock source for producing a digital waveform of a predetermined frequency and a direct-digital-synthesizer. The synthesizer has an input to receive the digital waveform and is operative to generate a resultant analog waveform. Prediction logic is coupled to the digital clock source and the synthesizer for determining the relative phase relationships between the digital waveform and the analog waveform. The prediction logic is responsive to a prediction clock having a clock frequency approximating that of said digital clock source.