Abstract: There is provided a system and method for the recordation an audio message, whereby the system converts the recorded message to a digital format, and stores the message on a record medium (18) integrally associated with the system. The record medium (18) with recorded message can be removably affixed to a wide range of objects. The system easily facilitates read, decode, and playback functionality for the recorded message without necessitating removal of the record medium (18) from the object to which it is affixed. Further, the system provides the functionality to store and forward audio messages in digital format to various computer systems (56) and computer-related devices.

Abstract: A method for making 0.25 micron semiconductor chips includes using TEOS as the high density plasma (HDP) inter-layer dielectric (ILD). More specifically, after establishing a predetermined aluminum line pattern on a substrate, TEOS is deposited and simultaneously with the TEOS deposition, excess TEOS is etched away, thereby avoiding hydrogen embrittlement of and subsequent void formation in the aluminum lines that could otherwise occur if silane were used as the HDP ILD.

Abstract: A method for making a semiconductor chip includes disposing copper interconnects adjacent via channels and then doping only the portions of the interconnects that lie directly beneath the via channels. Then, the via channels are filled with electrically conductive material. The impurities with which the interconnects are locally doped reduce unwanted electromigration of copper atoms at the interconnect-via interfaces, while not unduly increasing line resistance in the interconnects.

Abstract: To permit the use of a single remote control device in an AV system that can supply incompatible video signals, a switch box receives composite and S-video signals from an AV receiver, transforming these signals into the component video domain, and also receives component video signals from, e.g., a DVD player, with the output of the switch box being displayed on a television. The synchronization portion of the component video signal from the DVD player is sent to one of the input ports of the AV receiver as a trigger signal for comparison thereof with the synchronization signal in the switch box. When a user selects the AV receiver input port into which the trigger signal is input, the sense signal at the switch box is identical to the synchronization signal of the component video, and the switch box consequently sends the component video to the television. Otherwise, one of the video signals from the AV receiver is sent to the television.

Abstract: A disk surface asperities tester including a glidehead member having a piezoelectric sensor fabricated directly on the glidehead member. The piezoelectric sensors are useful in applications utilizing 70%, 50%, 30%, or smaller glideheads. The invention discloses a method for manufacturing sensors utilizing microchip fabrication techniques to form the piezoelectric sensors directly on glidehead surfaces, including standard Al2O3.TiC glideheads. The fabricated piezoelectric sensors are used in combination with signal processors to detect and analyze asperities in a disk drive surface.

Abstract: A method for improving the gate coupling in a flash memory core includes forming floating gates of memory element stacks by depositing a first polysilicon layer having relatively small grain size on a tunnel oxide layer and then depositing a second polysilicon layer on the first, the second polysilicon layer being made of relatively large hemispherical-grained (HSG) polysilicon crystals, which improves gate coupling. In contrast, owing to the relatively small size of its grains, the first layer of polysilicon advantageously establishes a relatively flat surface interface with the tunnel oxide layer that is between the memory stacks and the underlying silicon substrate. Conventional control gates are then established above the HSG layer.

Abstract: A method and device for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves forming a multi-graded lateral channel doping profile by dual halo implants annealed at different temperatures to improve the threshold voltage roll-off characteristics of MOSFETs of 50 nm or less. The method includes forming a spacer on the sidewalls of a gate, followed by forming source/drain regions by epitaxial growth followed by a deep source/drain implant and anneal. After removal of the spacer, the first angled deep halo implant through the space formed by removal of the spacer and a second annealing at a temperature lower than the first anneal occurs. A second angled halo implant and a third anneal at a temperature less than the second anneal is performed. The microelectronic chip is then silicided and the MOSFET is further completed.

Abstract: An ultra-thin body SOI MOSFET transistor and fabrication method are described which provide extended silicide depth in a gate-last process. The method utilizes the fabrication of a dummy gate, comprising insulation, which is replaced with an insulated gate after implantation, annealing, and the formation of silicide so that diffusion effects are reduced. By way of example, dummy gate stacks are created having insulating upper segments. Silicon is deposited on the wafer and planarized to expose the insulating segment. The junction is formed by implantation followed by annealing to recrystallize the silicon and to activate the junction. Silicide is then formed, to a depth which can exceed the thickness of the silicon within the SOI wafer, on the upper portion of the silicon layer. The segment of insulation is then removed and a gate is formed with a gate electrode insulated by high-k dielectric.

Abstract: A method for making a ULSI MOSFET includes depositing a high-k gate insulator on a silicon substrate and then depositing a field oxide layer over the gate insulator. The field oxide layer is masked with photoresist and the photoresist patterned to establish first gate windows, and the oxide below the windows is then etched away to establish first gate voids in the oxide. The first gate voids are filled with a first metallic gate electrode material that is suitable for establishing a gate electrode of, e.g., an N-channel MOSFET. Second gate voids are similarly made in the oxide and filled with a second gate electrode material that is suitable for establishing a gate electrode of, e.g., an P-channel MOSFET or another N-channel MOSFET having a different threshold voltage than the first MOSFET. With this structure, plural threshold design voltages are supported in a single ULSI chip that uses high-k gate insulator technology.

Abstract: A multiple port valve plate assembly for use with a vacuum drum in a labeling apparatus. The valve plate has a first stationary vacuum cavity which is supplied with one level of vacuum suitable for picking up a label segment from a cutter with limited tension. The valve plate has a second, floating cavity, which is supplied with another, higher level of vacuum suitable for firmly griping the cut label segment as an adhesive is applied to the label segment. The valve plate has a third stationary vacuum cavity for suitable for holding the label at a lower vacuum pressure while the label is being transferred to a container. The third cavity may be further divided into a label application segment with an even lower vacuum pressure. A pressure port is also provided adjacent the third cavity for facilitating release of the label from the vacuum drum as it contacts the container.

Abstract: A method of fabricating an improved flash memory device having core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer and oxide layer into the substrate to create source and drain regions, without using a self aligned etch. The flash memory device has an intermetallic dielectric layer placed over the core stacks and the periphery stacks. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device.

Abstract: The education intermediary system and method for facilitating an interested learner to have a worldwide choice of an instructor who is best matched with his expectations are disclosed. The education intermediary system comprises a first database and a first processing means. The first database contains data of a plurality of instructors. The first processing means receives a first set of data inputted by an interested learner and, based on selection criteria containing the first set of data, selects from the first database an instructor who is best matched with the selection criteria, and provides from the first database at least part of the data of the selected instructor to the interested learner.

Abstract: A method for fabricating a semiconductor interconnect structure having a substrate with an interconnect structure patterned therein, a barrier layer, a pre-seed layer, a seed layer, a bulk interconnect layer, and a sealing layer, and a device thereby formed. The barrier layer is formed using atomic layer deposition techniques. Subsequently, a pre-seed layer is formed to create a heteroepitaxial interface between the barrier and pre-seed layers. This is accomplished using atomic layer epitaxy techniques to form the pre-seed layer. Thereafter, a seed layer is formed by standard deposition techniques to create a homoepitaxial interface between the seed and pre-seed layers. Upon this layered structure further bulk deposition of conducting materials is done. Excess material is removed from the bulk layer and a sealing layer is formed on top to complete the interconnect structure.

Abstract: This invention relates to a refrigerator with a foldable table, wherein the table can be unfolded when it is needed and can be folded when it is not needed. So the product of the present invention has the functions of both a refrigerator and a table, and also can save some room space providing a more reasonable room layout.

Abstract: A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms first, which subsequently volumetrically contracts, thereby forming a titanium aluminide compound, with the contraction being absorbed by the aluminum. Because the alloy is reacted to form the metal compound prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced.

Abstract: A method of fabricating a semiconductor device, having a locally-formed metal oxide high-k gate insulator, involving: nitriding a substrate to form a thin silicon nitride layer; depositing a thin metal film on the thin silicon nitride layer; forming a localized metal oxide layer from the thin metal film, wherein the a thick nitride layer is deposited on the thin metal film, the thick nitride layer is patterned, the at least one exposed thin metal film portion is locally oxidized, by heating, wherein the oxidizing is performed by local laser irradiation; forming a gate stack having the localized metal oxide layer and a gate electrode, wherein the a thick gate material is deposited in the electrode cavity and on the localized metal oxide layer; the thick gate material is polished, thereby forming the gate electrode; and the thick nitride layer along with the at least one covered thin metal film portion are removed, thereby forming the gate stack; and completing fabrication of the device, and a device thereby fo