Abstract: An EEPROM cell and array of cells is disclosed having buried diffusion source/drain lines and buried diffusion erase lines. The cells further include coupling between the floating gate and control gate above the source/drain diffusion. The disclosed cell allows high packing density and operation at low voltages.

Abstract: Preferred embodiments include channel stop implants for CMOS devices by through field boron implants (152) after the field oxide (144, 145) has been grown and with the implant depth determined by the thin portions of the field oxide (145). Junction (154) breakdown is preserved by channeling the implant (152) to penetrate far below the junctions (154).

Abstract: A DRAM cell (8) having a storage node (18), a pass transistor (76) and a polysilicon word line (84) formed within an oxide isolated trench (68), thereby providing high soft error immunity. A write bit line (66) functions as the drain region (78) of the pass transistor (76) and is isolated from the substrate by a oxide isolation (64), thereby enhancing soft error immunity. The trench (68) includes an annular opening for providing intimate contact between the past transistor conduction channel (82) and the single crystal silicon substrate (36). During processing, the polysilicon conduction channel (82) of the pass transistor (76) is converted into single crystal silicon, thereby providing enhanced performance of the cell (8).

Abstract: A plasma etching process employs a halogen liberating gas to selectively etch a top semiconductor layer of a bilayer with respect to a bottom semiconductor layer. A fluorine rich gas reacts with a top germanium layer for removal thereof, while forming a passivating surface layer on a bottom silicon layer to inhibit the silicon' plasma reaction therewith.

Abstract: An electrically erasable, programmable read only memory (EEPROM) having an erase window directly overlying both a control gate layer (24) and a column line (12) is disclosed. Column lines (12) are implanted into a semiconductor substrate (16) and covered with a first insulating layer (18). A floating gate layer (20) overlies the first insulating layer (18) and is covered with a second insulating layer (22). The control gate layer (24) overlies the second insulating layer (22) and is covered by a third insulating layer (26). A passage (28) extends through the third insulating layer (26), control gate layer (24) and second insulating layer (22) and contains a sidewall insulator (30) on walls thereof. A tunnel oxide (32) resides within the passage (28) and is contacted by a programming electrode layer (34) which additionally overlies the third insulating layer (26) and fills the passage (28).

Abstract: Polysilicon gate insulated gate field effect transistors with threshold adjustment implants made after the gate oxide (156) and a split of the polysilicon gate (158) have been formed provides a shallow, tight dopant profile.

Abstract: The preferred embodiments include Schottky barrier diode (80) clmaped bipolar transistors for use in planar integrated circuits with the diode (80) being formed in a trench to increase junction area, reduce series resistance from junction to the buried layer (64), and reduce lateral extent of the extrinsic base (78).

Abstract: The invention provides an EPROM having a high quality dielectric to separate the floating gate from low quality dielectric layers used in the prior art by the method outlined as follows. First, the polycrystalline silicon floating gates are formed and partially patterned on the surface of a substrate. A thin thermally grown oxide layer is then formed over the entire array. The source/drain regions are then implanted through the thin silicon dioxide layer into the substrate. Next a thick silicon dioxide layer is deposited by chemical vapor deposition on the surface of the array. The surface of the array is then coated with photoresist which, because of its nature, provides a planarized surface on the top layer of photoresist. The photoresist and the silicon dioxide layer are then etched using an etching process which provides an etching ratio of 1:1 between photoresist and silicon dioxide. The photoresist is completely etched away thus leaving the planarized silicon dioxide surface.

Abstract: A memory cell (10) comprises a ferromagnetic gate (12) disposed above a source (18) and a drain (20) in a substrate (16). A magnetic field is created in the ferromagnetic gate (12) by producing a large current between the source (18 ) and drain (20). The orientation of the magnetic field will depend upon the direction of the current flow. To read information from the memory cell (10), a small current is passed from source (18) to drain (20); if the electrons (25) are deflected upwards towards the surface (24) of the substrate (16), a lesser current will result than if the electrons (25) are deflected downward towards the bottom of the channel (22). Hence, the magnetic orientation, and therefore the information stored within the memory cell (10), can be determined by the amount of current detected.

Abstract: A method of forming semiconductor devices wherein a gap is formed beneath the field oxide between the channel stop implant and source/drain regions in the moat or active element region to prevent or minimize encroachment of channel stop impurity toward the source/drain regions to form spurious pn junctions and/or reduce the active element region.

Abstract: The present invention provides a structure and method for fabricating that structure which provides increased capacitance over the prior art while occupying a minimum of surface area of the integrated circuit. The present invention accomplishes this by interleaving multiple capacitor plates to provide increased capacitance while occupying the same surface area as a prior art capacitor providing a fraction of the capacitance provided by the present invention. The present invention is fabricated by providing a capacitor stack which includes interleaved plates of material which may be selectively etched and which is separated by appropriate dielectric material. One portion of the stack is masked while one set of the interleave plates is etched. The etched portion of the interleave plates is filled by a suitable dielectric and a contact is made to the remaining plates. A different portion of the stack is then exposed to an etch which etches the other set of interleave plates.

Abstract: The disclosure relates to a method for low temperature (less than 120 degrees C.) hardening of photoresist pattern by providing a high power light beam consisting of light having a wavelength of about 300 nanometers and above which leads to crosslinking throughout the resist. A hot plate constant temperature (less than 120 degrees C.) is optionally used to accelerate the crosslinking reaction, thus incrasing throughput.

Abstract: A substrate bias voltage regulator (10) is disclosed having a voltage divider (22) for generating a reference voltage, a low gain stage (24) for developing a drive voltage independent of the supply voltage (V.sub.cc) and for driving a current source/mirror circuit (26). The current source/mirror circuit (26) operates in conjunction with a current sink circuit (30) for providing a logic output of the regulator (10) for controlling a substrate charge pump circuit (18). Connected to the current sink circuit (30) is a compensation circuit (32) for adjusting the drive to the current sink circuit (30) in response to transistor threshold voltage and temperature considerations.

Abstract: An upstanding sidewall conductor (38) is formed in a via (30) that is made in a thick oxide layer (28) to expose a polysilicon gate electrode (22). A thin insulator layer (42) is deposited over the sidewall conductor layer (38) and a central region (32) of the polysilicon electrode (22). A second conductive layer (44) is deposited in the via (30) so as to be in registry with the upstanding sidewall conductor (38) and the central region (32) of the polysilicon electrode (22). In this way, the capacitive coupling between electrode (22) and electrode (44) is enhanced.

Abstract: Silicon dioxide is deposited by low pressure chemical vapor deposition (LPCVD) from dichlorosilane plus nitrous oxide, using a larger concentration of dichlorosilane than of nitrous oxide.

Abstract: A transistor (14) having a plurality of sub-transistors (29a-f) includes a voltage controlling device (45). The voltage controlling device induces a current through an elongated gate (24) producing a voltage drop across the elongated gate (24) by providing a path between the gate and ground (32). The voltage drop across the elongated gate (24) sequentially reduces the gate voltage present at each of the sub-transistors (29a-f), thereby reducing the amount of current which the sub-transistors (29a-f) can conduct. The voltage controlling circuit (45) gradually reduces the current through the gate (24), thereby increasing the amount of current flowing through the sub-transistors (29a-f). The limiting of current through the output transistors (29a-f) for a predetermined time interval reduces the generation of output noise by controlling the rate at which current is changing in that output.

Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of the platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.

Abstract: A CMOS output pair provides rapid switching speed while avoiding excessive noise levels developed across the power supply parasitic inductance. Both the P-channel and N-channel transistors of the output pair actually comprise a plurality of sub-transistors with their source to drain current paths connected in parallel. As a result of novel RC coupling of a switching signal from gate to gate of either of the plurality of sub-transistors, the sub-transistors are caused to turn on sequentially. Since none of the sub-transistors is capable of supporting the current that must be carried by the totality of sub-transistors making up either the P-channel or N-channel transistor, the increments of current as each sub-transistor turns on are small relative to the total.

Abstract: A voltage reference circuit which includes a first diode having a first predetermined forward voltage drop as a function of current, a second diode having a second predetermined forward voltage drop as a function of current, lower by a preselected amount than said first diode voltage drop and connected to a voltage reference node and to one end of said first diode. A resistor is connected to the voltage reference node and to another end of the first diode such that the second diode and the resistor form a current path around the first diode. The arrangement is such that the temperature coefficient of voltage at the voltage reference node is less than that across the first diode.

Abstract: A method of processing an interlevel dielectric layer in a VLSI device having a plurality of leads which includes depositing a layer of photoresist over the dielectric layer. The photoresist is then patterned to open areas where interlevel contacts are to be formed and then heated to a sufficiently high temperature and for a sufficient time to remove solvents and obtain a desired slope surrounding the open areas. The photoresist and dielectric is etched to planarize the dielectric surface, to expose the underlying leads and to remove all of the photoresist.