Abstract: A circuit is designed with a decoder circuit (10), responsive to a first input signal (81) having a first voltage range, for producing a first output signal. An output circuit (11), responsive to the first output signal, produces a second output signal (26) having a second voltage range. The second voltage range includes a voltage less than a least voltage of the first voltage range and a voltage greater than a greatest voltage of the first voltage range.

Abstract: A word or row line (38a, 38b) associated with at least one row of memory cells in an integrated circuit memory array (10) having a plurality of word lines is driven by a drive/boot generator signal (RLXH) by first generating this drive signal using a drive signal generator (20) that is formed in a peripheral area (14) of the chip (10). The drive signal (RLXH) is transmitted to each of a plurality of predecoders (40) that are formed within a memory cell array area (12) of the chip (10). At least one of the predecoders (40) is actuated to transmit the drive signal (RLXH) onto a selected one of a plurality of predecoder output lines (RDD0-RDD3) in response to predetermined addressing or row factor signals (RF0-RF19). The drive signal (RLXH) is transmitted on a selected predecoder output line (44) to each of a plurality of decoders (36) formed within the array area (12).