Abstract: The present invention describes a spread spectrum communication system wherein the frequency of carriers and the code channels of the carriers or both for transmission to a given remote station user vary in time. This provides for a direct sequence spectrum communications system which changes frequency or code channel according to a predetermined pattern. The code channels and frequencies can be determined in accordance with a deterministic function or based upon a subset of the data to be transmitted. A receiver structure is also described for receiving the same.

Abstract: A method for sending an uplink order to active set base stations is disclosed. A new mode of operation for a wireless communication device is determined. A transmission is sent on an uplink control channel to active set base stations that indicates the new mode. The transmission from the wireless communication device is received on the E-DPCCH. It is determined if the transmission is an uplink order. The new mode of operation is transitioned to. Subsequent transmissions from the wireless communication device are interpreted using the new mode of operation if the transmission is an uplink order.

Abstract: A method for interference reduction is described. A sampling frequency is selected for a digital-to-analog converter (DAC) so that images within a DAC output signal do not interfere with one or more receivers. A sample rate is adjusted of an input signal that is provided to the DAC to match the sampling frequency for the DAC.

Abstract: Systems and techniques are disclosed wherein a gated pilot signal can be re-acquired faster by searching a last known pilot offset and/or searching a last coset in which the last pilot signal was found.

Abstract: Techniques for identifying and suppressing frequency spurs in a signal are disclosed. In an embodiment, an incoming signal is rotated by a frequency related to a spur frequency, and an estimate of the content of the rotated signal is derived. The estimate may be subtracted from the rotated incoming signal, and the result de-rotated by the spur frequency. In an embodiment, the incoming signal may be rotated such that the spur is centered at DC. In an alternative embodiment, the estimate may be de-rotated before being subtracted from the original incoming signal. Techniques for addressing multiple spurs using serial and parallel architectures are disclosed. Further disclosed are techniques for searching for the presence of spurs in an incoming signal, and tracking spur frequencies over time.

Abstract: An amplifier with integrated filter (e.g., an LNA) is described. In one design, the amplifier may include a gain stage, a filter stage, and a buffer stage. The gain stage may provide signal amplification for an input signal. The filter stage may provide filtering for the input signal. The buffer stage may buffer a filtered signal from the filter stage. The amplifier may further include a second filter stage and a second buffer stage. The second filter stage may provide additional filtering for the input signal. The second buffer stage may buffer a second filtered signal from the second filter stage. All of the stages may be stacked and coupled between a supply voltage and circuit ground. The filter stage(s) may implement an elliptical lowpass filter. Each filter stage may include an inductor and a capacitor coupled in parallel and forming a resonator tank to attenuate interfering signals.

Abstract: A method for minimizing search time and disruption of current service on an originating frequency during a frequency search excursion to a target frequency as part of an inter-frequency hard handoff between cells on different RF CDMA channels. Disruption of service on the current frequency during the frequency search excursion to the target frequency is minimized by increasing the amount of power allocated to other symbols of two consecutive frames impacted by the search excursion as a function of the search excursion time. The mobile station tunes to a target frequency and collects chip samples, which are stored in a memory buffer. The mobile station returns to the originating frequency to process the collected samples.

Abstract: Quiescent supply current (IDDQ) verification, prediction, and debugging of low power semiconductor devices are enhanced by IDDQ defect diagnosis. If all IDDQ patterns fail verification, per module analysis is performed to sort out potential module design issues or cell constraint issues. For issues of missing constraints, and cell design or implementation issues leading to extra leakage that could be avoided by adding constraints, there are usually IDDQ patterns that correlate with expectations, and patterns that do not, due to the random nature of unconstrained scan cell values as determined by the pattern generation tool. Differentiating good and bad IDDQ patterns can identify root causes of IDDQ issues and additional constraints to fix the bad IDDQ vectors. These verification procedures are achieving IDDQ test success and short time to market, as well as significantly faster time to volume and improved yields because of having a higher quality and better-controlled IDDQ test.

Abstract: In one embodiment, the present invention comprises a vocoder having at least one input and at least one output, an encoder comprising a filter having at least one input operably connected to the input of the vocoder and at least one output, a decoder comprising a synthesizer having at least one input operably connected to the at least one output of the encoder, and at least one output operably connected to the at least one output of the vocoder, wherein the encoder comprises a memory and the encoder is adapted to execute instructions stored in the memory comprising classifying speech segments and encoding speech segments, and the decoder comprises a memory and the decoder is adapted to execute instructions stored in the memory comprising time-warping a residual speech signal to an expanded or compressed version of the residual speech signal.

Abstract: Switchable voltage level supplies for circuitry in a multi-mode communications chipset are disclosed. In an embodiment, a first voltage level is supplied to TX circuitry operating in a first mode having a first set of linearity and/or noise requirements. A second voltage level lower than the first voltage level is supplied to TX circuitry operating in a second mode having a second set of linearity and/or noise requirements looser than the first set of requirements. The first mode may be operation according to the GSM standard, and the second mode may be operation according to the W-CDMA standard.

Abstract: A method for handling a signaling message that specifies transmission rate restrictions may include operating in a first state. The method may also include receiving the signaling message from a network. The signaling message may include an activation time, the transmission rate restrictions and the control duration. The method may also include receiving a state transition trigger to operate in a second state. The method may also include determining the user equipment's behavior regarding the transmission rate restrictions upon receiving the state transition trigger.

Abstract: Techniques to forward unsolicited messages from an (IS-2000) CDMA radio network via an HDR radio network to an access terminal. A session is first established between the access terminal and the HDR radio network. During session establishment or thereafter, the access terminal indicates to the HDR radio network an interest in receiving unsolicited messages from the CDMA radio network. The access terminal typically also registers with the CDMA radio network. Thereafter, unsolicited messages can be sent from a mobile station controller (MSC) to the HDR and CDMA radio networks, or sent from the MSC to the CDMA radio network, which then forwards the messages to the HDR radio network. The HDR radio network encapsulates the unsolicited messages and sends the encapsulated messages to the access terminal. The forwarding of unsolicited messages allows the CDMA radio network to communicate with an access terminal.

Abstract: A switched-capacitor decimator that can attenuate undesired signal components at odd harmonics of an output sample rate is described. In one design, the switched-capacitor decimator includes at least one sampling capacitor and multiple switches. For each sampling capacitor, the top plate is charged with a first input signal when the capacitor is selected for top charging, and the bottom plate is charged with a second input signal when the capacitor is selected for bottom charging. For each sampling capacitor, the top plate provides its stored charges to a first output signal and the bottom plate provides its stored charges to a second output signal when the capacitor is selected for reading. The switches couple the at least one sampling capacitor to the first and second input signals for charging and to the first and second output signals for reading.

Abstract: An electronic device is provided for generating or utilizing one or more cycle-swallowed clock signals derived based on one or more first clock signals. The device includes a module configured to receive a first clock signal having a first frequency. The module is configured to generate a second clock signal having a second frequency and configured to swallow one or more clock cycles of the first clock signal in generating the second clock signal. The first clock signal has even cycles, and the second clock signal has uneven cycles. The first frequency is greater than the second frequency. The module may include a cycle-swallowing counter. A method and a computer-readable medium are also provided.

Abstract: The present invention comprises a method of communicating background noise comprising the steps of transmitting background noise, blanking subsequent background noise data rate frames used to communicate the background noise, receiving the background noise and updating the background noise. In another embodiment, the present invention comprises an apparatus for communicating background noise comprising a vocoder, at least one smart blanking apparatus operably connected to the vocoder, a de jitter buffer operably connected to the smart blanker; and a network stack operably connected to the input of the de jitter buffer and the an output of the smart blanking apparatus.

Abstract: The present patent application comprises a linear transconductor having at least one input and at least one output, comprising a differential amplifier having a plurality of transistors and a plurality of inputs, wherein a difference of input signals is amplified, a cascode circuit having a plurality of transistors, wherein the transistors are operably connected to the differential amplifier, wherein reverse isolation between an input and an output of the linear transconductor is improved by decoupling the input and the output of the linear transconductor by mounting at least one transistor of the plurality of transistors of the cascode circuit as a common-gate stacked on the at least one transistor of the differential amplifier, an active load having a plurality of transistors operably connected between the cascode circuit and supply voltage, and an auxiliary device operably connected to the connection between the active load, the cascode device and ground.

Abstract: An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks. The apparatus further comprises a phase locked loop (PLL), such as a digital PLL (DPLL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal. By maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, the continual and effective operation of the phase locked loop (PLL) is not significantly disturbed while changing the reference clock. This may be used to control the power consumption of the apparatus.

Abstract: Methods and apparatus are disclosed herein for providing incremental redundancy in a wireless communication system to aid in error recovery. One or more redundancy versions are sent on different carriers than the primary version of information to be transmitted. At the receiver end the redundancy versions may be combined using hard or soft combining techniques, including selection combining, selective soft combining or soft combining.

Abstract: A local oscillator includes a phase-locked loop. The phase-locked loop includes voltage controlled oscillator (VCO) and a novel VCO control circuit. The VCO control circuit may be programmable and configurable. In one example, an instruction is received onto the VCO control circuit to change the power state of the VCO. The instruction is issued by other circuitry in response to a detected change in RF channel conditions (for example, a change in a signal-to-noise determination) in a cellular telephone. In response, the VCO control circuit outputs control signals that gradually widen the loop bandwidth of the PLL, then gradually change the VCO bias current to change the VCO power state, and then narrow the loop bandwidth of the PLL back to its original bandwidth. The entire process of widening the PLL bandwidth, changing the VCO power state, and narrowing the PLL bandwidth occurs while the PLL remains locked.

Abstract: In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.