Abstract: This invention provides a method of using an electron beam exposure system having an electron beam with a variable shape to form patterns in a layer of resist on a substrate, a mask substrate or an integrated circuit wafer, while maintaining adequate critical dimension control and beam stability. This is accomplished by setting the electron beam to a fixed square beam with a width set to provide optimum XY critical dimension control for exposing a frame pattern surrounding the original pattern. The frame pattern has a width of a first distance and surrounds the outer perimeter of the original pattern. This provides optimum XY critical dimension control at the outer perimeter of the original pattern. The remainder of the exposure field, which is the exposure field with the original pattern and the frame pattern subtracted away is exposed using an electron beam having a variable size and shape.

Abstract: A method of planarizing wafers using shallow trench isolation is described. The method uses a very hard polishing pad and chemical mechanical polishing with no additional etching required. Trenches are formed in a substrate and filled with a trench dielectric, such as silicon dioxide deposited using high density plasma chemical vapor deposition. A layer of resist is then formed on the layer of trench dielectric. The wafer is then planarized using chemical mechanical polishing and a polishing pad having a hardness of at least Shore “D” 52. The hard polishing pad avoids scratch marks on the trench dielectric, the substrate surface, or any other materials deposited on the substrate surface.

Abstract: Low cost antennas formed of conductive loaded resin-based materials. The conductive loaded resin-based materials are resins filled with conductive materials to provide a material which is a conductor rather than an insulator or body. The conductive materials comprise a resin-based structural material loaded with micron conductive powders or micron conductive fibers to provide a composite which is a conductor rather than an insulator. Virtually any antenna fabricated by conventional means such as wire, strip-line, printed circuit boards, or the like can be fabricated using the conductive loaded resin-based materials. The antennas can be formed using methods such as injection molding, overmolding, or extrusion.

Abstract: This invention describes methods of using pattern fracture rules to form mask pattern segments and the mask for the mask pattern segments. The mask pattern segments have optical proximity correction and are separated into regular pattern elements and optical proximity correction elements. Regular fracture elements and special fracture elements are used. The special fracture elements are parallel to the regular fracture elements, perpendicular to the regular fracture elements, or both parallel to and perpendicular to the regular fracture elements. The special fracture elements are used to define the regular pattern elements and prevent the formation of resist residue in the completed mask. The optical proximity correction elements are formed using the regular fracture elements.

Abstract: A method of forming a resistor is described which achieves improved resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilicon. The resistor has a rectangular first, second, third, fourth, and fifth resistor elements. A layer of protective dielectric is formed over the first, second, and third resistor elements leaving the fourth and fifth resistor elements exposed. The conducting material in the exposed fourth and fifth resistor elements is then changed to a silicide to form low resistance contacts between the second and fourth resistor elements and between the second and fourth resistor elements. The second and third resistor elements are wider than the first resistor element and provide a low resistance contacts to the first resistor element. This provides a low voltage coefficient of resistance and thermal process stability for the resistor.

Abstract: Antennas and methods of forming the antennas having a very low profile and a built in ground plane are described. The antenna elements are formed of conducting material on a layer of dielectric material, such as an integrated circuit board. The antenna elements are mounted on a ground plane having a number of shorting elements between one of the antenna elements and the ground plane. In some embodiments the antenna elements are on a single side of the layer of dielectric material. In other embodiments the antenna elements are formed on both the top and bottom surfaces of the layer of dielectric material. The self contained ground plane makes the antenna performance independent of proximity to conducting or non conducting surfaces.

Abstract: A phase shifting mask set and method of using the phase shifting mask set to pattern a layer of negative photoresist. The mask set comprises a first phase shifting mask and a second phase shifting mask. The first and second phase shifting masks have regions of 90° phase shift and −90° phase shift in the contact hole regions of the masks. In the second phase shift mask the phase shift regions are rotated 90° spatially with respect to the phase shift regions of the first phase shift mask. A layer of negative photoresist is exposed with the first and second phase shift masks and developed to form the photoresist pattern used to form contact holes.

Abstract: An output stage and method for a charge pump circuit which substantially reduces the degradation of the output voltage. A first NMOS transistor has its source connected to an input node and its drain connected to a second node. A second NMOS transistor has its source connected to the input node, its gate connected to the drain of the first NMOS transistor, and its drain connected to the gate of the first NMOS transistor. A capacitor is connected between a second clock signal and the drain of the second NMOS transistor. Another capacitor is connected between a first clock signal and an intermediate node. The key part of the invention is a diode pair connected anode of one to the cathode of the other and inserted between the intermediate node and the drain of the first NMOS transistor.

Abstract: A method of adding optical proximity correction, OPC, to a base pattern is described. A base pattern is represented by a digital base pattern data file. A first OPC data file representing a first OPC pattern which adds pattern width at exterior corners of the pattern and a second OPC data file representing a second OPC pattern which reduces pattern width at interior corners of the pattern are formed. The final data file results from the logical subtraction of the second OPC data file from an interim data file formed by the logical OR of the base pattern data file and the first OPC data file. The final data file can be used to form masks or to inspect masks.

Abstract: A layer of low k dielectric is formed on a substrate having a conducting electrode formed therein. A via hole is formed in the low k dielectric exposing the conducting electrode. A thin layer of amorphous silicon is deposited on the layer of low k dielectric and on the sidewalls and bottom of a via hole. A layer of resist is then formed and patterned with a trench pattern. A trench is etched in the layer of low k dielectric directly over the via hole using the patterned layer of resist. The patterned layer of resist is then stripped and the trench and via hole are filled with conducting material. The layer of amorphous silicon prevents amine radicals, NHx, which can be released from the low k dielectric, especially during the via hole etching, from interacting with the resist and forming resist scum resulting in via poisoning.

Abstract: A method of producing defect free resist images from defective phase shifting or extreme ultraviolet masks is described. The method uses supplemental radiation to achieve direct repair of the resist image. Pinhole type of defects in opaque pattern elements, which would cause overexposed regions of resist and can readily be repaired on the mask, are first repaired directly on the mask before the mask is used in the exposure of a layer of resist. The remaining defects on the mask are left as they are and not repaired. The layer of resist is then exposed using the partially repaired mask. The remaining mask defects will cause unexposed latent images in the layer of resist. These unexposed regions of the resist are then exposed using supplemental radiation thereby correcting the exposure of the layer of resist. The layer of resist is then developed to form a defect free resist image.

Abstract: A molded flexible circuit assembly and method of forming a molded flexible circuit assembly which use a molded stiffener, and do not require any additional type of stiffener, are described. A molded stiffener is formed on a flexible tape at the same time molded encapsulation units are formed to encapsulate circuit die which are attached to the flexible tape. The molded stiffeners provide adequate rigidity for processing of the molded flexible circuit assembly. When the stiffeners are no longer needed they are removed at the same time the mold runners are removed. No additional processing steps are required for either the formation or removal of the molded stiffeners.

Abstract: A method and computer program for dynamic matching of wafer lots waiting for processing and available tools to maximize wafer output. Wafer lot information and tool capability and availability is provides. Priority wafer lots are processed first. All permutations of the remaining non priority lots and available tools are then formed. The longest process time for each permutation is then calculated. A permutation wafers per hour, PWPH, equal to the total number of wafers processed for each permutation divided by the longest process time for that permutation is calculated. If only one permutation has the highest PWPH that permutation is selected for processing. If more than one permutation has the highest PWPH the total wafers per hour, TWPH, equal to the sum of the wafer per hour capability of each tool in the permutation is calculated for those permutations. Any permutation with the highest PWPH and TWPH is selected for processing.

Abstract: A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions. The control gate has a concave top surface which intersects with the sidewalls to form a sharp edge. The cell is programmed by charging the floating gate with electrons by means of hot electron injection from the channel into the floating gate. The cell is erased by discharging the excess electrons from the floating gate into the control gate using Fowler-Nordheim tunneling. The sharp edge at the intersection of the concave top surface and the sidewalls of the floating gate produces a high electric field between the control gate and the floating gate to accomplish the Fowler-Nordheim tunneling with only moderate voltage differences between the floating gate and control gate.

Abstract: A charge pump voltage regulating circuit which uses a constant current generator and a second current generator, controlled by the output voltage of the charge pump circuit. The current from the constant current generator is divided between the input to a current controlled oscillator and the second current generator. When the output voltage of the charge pump circuit increases the current in the second current generator increases, the current flowing into the current controlled oscillator decreases, the frequency of the clock signals supplied to the charge pump circuit decreases, and the output voltage of the charge pump circuit decreases. When the output voltage of the charge pump circuit decreases the current in the second current generator decreases, the current flowing into the current controlled oscillator increases, the frequency of the clock signals supplied to the charge pump circuit increases, and the output voltage of the charge pump circuit increases.

Abstract: An apparatus and method for developing a selectively exposed resist pattern, on an integrated circuit wafer, which avoids damage to the resist pattern and allows greater freedom in the choice of resists. Developer is placed on a selectively exposed layer of resist for a first time. The layer of resist and developer are then immersed in a cleaning liquid time for a second time to stop the developing action and remove the developer. As an option, ultrasonic power can be delivered to the wafer or the cleaning liquid while the layer of resist is immersed in the cleaning liquid. The cleaning liquid is then removed from the layer of resist, now a resist-pattern, and the wafer and resist pattern is placed in a vacuum for drying. As another option, heat can be applied to the wafer and resist pattern while they are in the vacuum. The wafer and resist pattern are then removed from the vacuum for further processing.

Abstract: A design for a magnetic write head having multi-layer stitched poles, a small throat height, and a recessed yoke design is described. The write head is formed of a number of planar layers and in one embodiment the write head also has a planar top surface. In another embodiment the planarity of the top layer is disturbed in order to provide an additional wiring layer. The magnetic write head is formed on a layer of ferromagnetic material which can also be used as a shield layer for a read head combined with the write head. A first pole piece has a notch which defines the throat height of the write head. A second pole piece, recessed from the air bearing surface plane, is magnetically stitched to the first pole piece. A third pole piece, further recessed from the air bearing surface plane, is magnetically stitched to the second pole piece.

Abstract: A method is disclosed for smoothing the top surface of a layer of polysilicon which, as deposited, has a rough top surface due to the formation of polysilicon grains. A polymer, such as CxFyBrz, is deposited using chemical vapor deposition. The polymer layer has a thickness large enough so that the top surface of the polymer is at least a critical distance above the peaks of the grains on the top surface of the layer of polysilicon. The layer of polymer and part of the layer of polysilicon are then etched away using an etch back method which etches the polymer and polysilicon at the same etch rate. This results in a layer of polysilicon having a smooth top surface and the same thickness over the entire layer of polysilicon.

Abstract: A mask and method of forming a mask for forming electrode patterns having both closely spaced lines and lines with greater separation between them. The mask uses a pattern formed using attenuating phase shifting material for the region of the mask with lines with greater separation and a binary pattern formed using opaque material in the region of the mask with closely spaced lines. The mask design data is used to determine the mask regions using attenuating phase shifting material and the regions of the mask using a binary pattern. The mask is illuminated using off axis illumination, preferably quadrapole off axis illumination. The mask is formed using electron beam exposure of a resist using more than one exposure dose so that only one layer of resist is required to form the two regions of the mask one using attenuating phase shifting material and one using a binary pattern.

Abstract: A mask set of two masks and a method of using these masks in a double exposure to avoid line shortening due to optical proximity effects is described. A pattern having pattern elements comprising a number of line segments, wherein each of the line segments has one or two free ends which are not connected to other mask pattern elements is to be transferred to a layer of resist. A first mask is formed by adding line extensions to each of the free ends of the line segments. A cutting mask is formed comprising rectangles enclosing each of the line extensions wherein one of the sides of said rectangles is coincident with the corresponding free end of said line segment. The first mask has opaque regions corresponding to the extended line segments. The cutting mask has transparent regions corresponding to the cutting pattern. In another embodiment a pattern having pattern openings comprising a number of line segments.