Abstract: A method and metal test pattern for monitoring metal corrosion susceptibility for integrated circuit wafers. Test patterns having an array of metal circles to simulate contact regions, an array of metal strips to simulate electrode regions, and a blanket metal layer to simulate bulk metal regions are formed. A first number of defects per unit area for the test patterns is measured, using a defect scan system. The test pattern wafers are then subjected to environmental stress conditions for a first time and a second number of defects per unit area for the test patterns is measured, again using a defect scan system. The difference between the second number and the first number is compared with a critical number. If excessive corrosion occurs the process for producing wafers is corrected before continuing to process product wafers.

Abstract: A mask and method of forming a pattern on an integrated circuit wafer having regions of dense line/space patterns and regions of isolated lines or widely spaced line/space patterns. The mask uses a binary mask pattern to form the dense line/space region and an attenuating phase shifting mask pattern to form the isolated line or widely spaced line/space region. Scattering bars are used in the widely spaced line/space region of the mask to improve depth of focus. The method uses the mask in a projection exposure system to expose a layer of photosensitive dielectric on an integrated circuit wafer.

Abstract: This invention provides a digital color encoder for digitizing color video signals. The encoder forms a digitized color video signal using logic function processing of the digitized luminance signal and color difference signals. The encoder provides an output signal equivalent to the luminance signal added to the color difference signals modulated by triangular wave functions and sampled at the sampling frequency. The sampling frequency is eight times the crominance subcarrier frequency. An analog video signal can easily be recovered from the digital video signal because the fundamental frequency of the triangular wave is easily separated from the higher order harmonics.

Abstract: This invention provides an improved process latitude mask for forming contact or via hole openings in a photoresist masking layer in the fabrication of semiconductor integrated circuits. The invention also provides a method of forming contact or via hole openings in a photoresist masking layer using an improved process latitude mask. The improved process latitude mask, called a dot mask, uses an opaque blocking area formed in the center of the primary opening in a projection mask for forming contact or via hole openings in a photoresist layer. The opaque blocking area is equal to or less than the area of the primary opening divided by nine. The opaque blocking area is small enough so that it will not form an image in the photoresist layer. The opaque blocking area modifies the light intensity profile at the photoresist layer in a manner which improves process latitude.

Abstract: This invention provides a method of preventing contact autodoping and supressing tungsten silicide peeling during the reflow cycle for a borophosphosilicate glass insulating layer during fabrication of large scale integrated circuits. The invention uses a thin oxide layer to protect the contact areas during the reflow cycle. The thin oxide layer is thin enough to allow satisfactory reflow of the borophosphosilicate glass insulating layer and thick enough to prevent autodoping and tungsten silicide peeling. The thin oxide layer is also thin enough so that process time required to remove the thin oxide layer is not a significant increase in process time. The thin oxide layer thickness is controlled by depositing a helium diluted tetraethoxysilane vapor and oxygen using chemical vapor deposition.

Abstract: The invention relates to a method of forming an improved MOSFET device structure for use in ultra large scale integration devices. A local self-aligned anti-punchthrough region is formed directly under the gate electrode using ion implantation. The local anti-punchthrough region reduces the expansion of the depletion region in the channel and thereby increases the punchthrough voltage. The local anti-punchthrough region is self-aligned with the gate electrode and source/drain region so that critical spacings are maintained even for sub micron devices. Channel mobility is not degraded and the source and drain junction capacitances are reduced. The invention can be used in either N channel or P channel MOSFET devices, and in either LDD (light doped drain) or non-LDD devices.