Abstract: Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

Abstract: A method of performing the multiplexing of data streams in a packet network by initializing the address pointers in an output queue to point to their own addresses. Then, select a data packet from an input queue and determine whether the preferred location for its pointer in the output queue is occupied. If that location is occupied, go to the address pointed to by the address pointer for that location, and if not occupied, store the pointer to the input stream data in that location.

Abstract: Decoding an encoded block of data is accomplished by partitioning the block into a first and a second sub-block and performing forward and backward iterative calculations on the sub-blocks in separate processes. Based on results of the iterative calculations an output matrix may be calculated for each sub-block. The outputs may be combined.