Abstract: A computer-implemented system, method, and user interface for searching and organizing information, particularly large information sets such as those found on the Internet and World Wide Web. Information is organized and searched according to content, and this organization is reflected directly in the user interface provided to users for searching as well as the search results they are shown.

Abstract: A media agent that monitors multiple broadcast transmissions and a method for the same. The media agent establishes connections with broadcast transmissions and then identifies characteristics of the media content contained within the broadcast transmission. The association between the identified characteristic of the media content and the connected broadcast transmission is maintained to allow the information gathered from the broadcast transmission to be used meaningfully.

Abstract: Macroblock types of macroblocks of a video picture are encoded by adaptively employing codewords of codeword tables, based at least in part on one or more macroblock type related characteristics of one or more neighboring macroblocks of interest. The codewords may be variable in length. The one or more macroblock type characteristics may include a most common macroblock type characteristic of the neighboring macroblocks of interest. The adaptive employment of the codeword tables may be further based on a picture type of the picture of which the macroblocks are members. Decoding may be performed in an inverse manner.

Abstract: Large integers may be stored according to byte-stable variable-length encoding systems and methods, eliminating the need to store many leading-zero bits in large integers. Such a byte-stable variable-length integer encoding scheme may represent identical sequences of numbers in a consistent byte pattern within a byte stream, preserving the redundancy of the data and allowing for improved compression rates.

Abstract: Ideas, groups of ideas, projects, documents, and related materials may be depicted, organized, modified, and shared according to Idea Page systems, methods, and user interfaces. Published workflow templates may additionally be copied into a user context, modified, and depicted in a multi-level visual space, including first-level ideas organized and visually arranged in a first-level idea page, and second-level ideas organized and visually arranged in a second-level idea page.

Abstract: A layered media stream comprising media information layers of different priorities may be adaptively distributed by transmitting at least one of the media information layers to a client on a time-windowed basis. Within each time window, the transmission of the media information layers is attempted in priority order and lower priority layers are transmitted as network conditions allow.

Abstract: A circuit and method for achieving compressed distributions of erased cell threshold voltages in an EEPROM array is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for pre-programming operations before a bulk erase can take place. By eliminating the need to pre-program the memory array before each erasure, the process provides a signicant improvement for low power applications, because battery life is extended and write cycle time is enhanced.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: A circuit and method for achieving compressed distributions of erased cell threshold voltages in an EEPROM array is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for pre-programming operations before a bulk erase can take place. By eliminating the need to pre-program the memory array before each erasure, the process provides a signicant improvement for low power applications, because battery life is extended and write cycle time is enhanced.

Abstract: A test circuit for observing charge retention characteristics of cells in a flash memory array is disclosed. Unlike prior art structures, the present circuit monitors both charge loss and charge gain of cells in the array. In this way, cells having conduction thresholds below a desired target threshold and cells having conduction thresholds above a desired target threshold can both be observed. The circuit includes a regular memory array, and a mirror array formed with devices having opposite channel types to the regular array. By identifying and evaluating more accurately the threshold characteristics of a particular cell design or cell process, improvements can be made to such designs and processes in a more rapid and optimal fashion.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: A new hybrid magnetic spin injected-FET structure can be used as a memory element for the nonvolatile storage of digital information, as well as in other environments, including for example logic applications for performing digital combinational tasks, or a magnetic field sensor. The hybrid FET uses ferromagnetic materials for the source and drain, and like a conventional FET, has two operating states determined by a gate voltage, "off" and "on". The ferromagnetic layers of the hybrid FET are fabricated to permit the device to have two stable magnetization states, parallel and antiparallel. In the "on" state the spin injected FET has two settable, stable resistance states determined by the relative orientation of the magnetizations of the ferromagnetic source and drain.

Abstract: A modified Hall Effect device can be used as a memory element for the nonvolatile storage of digital information. The novel device includes a ferromagnetic layer that covers a portion of a Hall plate and is electrically isolated from the Hall plate. The ferromagnetic layer on the Hall plate can be changed by an externally applied field, and permits the device to have two stable magnetization states (positive and negative) along an anisotropy axis, which can correspond to two different data values (0 or 1) when the device is used as a memory element. In another embodiment of the invention, the Hall plate is integrated with a conduction channel of a FET, and the ferromagnetic layer is incorporated in proximity to, or as part of the gate over the conducting channel. This device can be described as a "ferromagnetic gated FET.

Abstract: A new magnetic spin transistor is provided. This spin transistor can be used as a memory element or logic gate, such as an OR, AND, NOT, NOR and NAND gate. The state of the magnetic spin transistor logic gate is set inductively. This new magnetic spin transistor/gate can be operated with current gain. Furthermore, inductive coupling permits the linking of multiple spin transistors and spin transistor gates to perform combinational tasks. A half adder embodiment is specifically described, and other logic gates and combinations of half adders can be constructed to perform arithmetic functions as part of a microprocessor.

Abstract: A new nonvolatile hybrid memory cell is provided. The cell is comprised of a magnetic spin transistor storage element and one or two FET isolation elements. The magnetic spin transistor stores data indefinitely while drawing zero quiescent power. The FET is operated as a voltage controlled resistor, isolating the cell with a large electrical impedance when not powered and accessing the contents of the cell with a low impedance path when addressed by an appropriate voltage select signal. The cell can be used in an array of cells in a nonvolatile random access memory.