Abstract: A functional verification system suited for verifying the function of non-cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

Abstract: Functional verification system enabling the state of difference signals to be traced. The signals represent the outputs resulting from the evaluation of combinatorial blocks and/or a plurality of state elements forming a target design. The combinatorial blocks and/or a plurality of state elements may be grouped into multiple clusters, with each cluster being identified by a cluster identifier. The tracing circuit may include a mask memory, a previous state memory, and trace controller. Each of the mask memory and the previous state memory may contain a number of locations equal to the number of clusters such that the relevant mask and previous state information may be accessed based on the cluster identifier. The trace controller receives evaluated outputs for a cluster at bit positions specified by a corresponding mask. The trace controller compares the received bits with the previous values, and generates an entry in a trace buffer to record any changes.

Abstract: A functional verification system suited for verifying the function of cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding to the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

Abstract: A functional verification system which can be used to evaluate either cycle based designs or non-cycle based designs. A target design is partitioned into multiple clusters, with a combinatorial block in each cluster being assigned to an evaluation unit. A flow control memory stores data indicating the sequence in which the clusters are to be evaluated. The evaluation units evaluate combinatorial blocks within a cluster in parallel. A cluster control memory indicates the manner in which a register is to be modified upon the evaluation (and results) of each cluster. The instructions in the flow control memory may be designed to examine the contents of the register and evaluate the clusters in different sequences depending on the content of the register. Evaluation of a loop of a non-cycle based design can thus be terminated based on the contents of the register.

Abstract: A functional verification system which provides information as to whether a signal has reached all possible states. For example, in the case of a signal with 0 and 1 as possible states, a 2 bit variable is initialized to 00. When a value of 1 is received for the signal, the first bit is set to 1 and when a value of 0 is received for the signal, the second bit is set to 1. Accordingly, by examining the two bits, one may determine whether the signal has attained one or both of 0 and 1 states.

Abstract: A flexible scheduler in an ATM switch. The scheduler enables each connection to be served fairly according to associated quality of service parameters, while enabling several other features. A connection can be shaped while minimizing additional memory and processing requirements. Specifically, the conformance time of cells of a connections need not be stored when significant backlog exists in the transmission of the cells. The shaping rate can be dynamically varied. Sequence of cells forming a frame are buffered in the ATM switch until the end of frame cell is received. All the cells of a frame are then sent in quick succession.

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.

Abstract: A switch guaranteeing a minimum amount of memory space for desired connection while allowing efficient dynamic change of maximum memory space that can be used by a connection. Only an amount of memory space which is required for guaranteeing the minimum amount of memory space is reserved. When the reserved space is decremented due to new cells being received on connections, the maximum memory space reserved for each connection is dynamically increased. For multicast connections, only a single copy of the cell data is stored even though a multicast cell is transmitted on several ports. Multicast cells can also be processed using the same signals used for processing unicast cells.

Abstract: A receiver to recover data encoded at high speed in a signal over a serial communication channel. A static phase determination circuit indicates whether the signal is early, late or neutral relative to a sampling clock. The sampling clock is used to oversample the signal to generate multiple samples. A token analyzer examines the transitions around a current symbol to determine any short term phase shifts of the boundaries between symbols. The short term phase shifts and the static phase together may be used to accurately select the samples representing the symbols without requiring extensive processing.

Abstract: An automatic sampling control system for digital monitors. A clock generation circuit generates a sampling clock. A phase controller modifies the phase of the sampling clock by a phase amount. An ADC samples a frame of an analog display signal to generate digital samples. A value which is a function of the samples is generated. The function generally generates a larger value with correspondingly large sample values. The phase amount is modified for successive image frames until a maximum function value is generated. When successive image frames do not change substantially in image content, the phase amount represents the optimal phase change for the sampling clock. If the image content is changing substantially, the phase adjustment may be disabled.

Abstract: A television system (TV) which enables a user to view display represented by a television signal as well as to access data network applications. The TV includes an on-screen-display (OSD) controller which stores the network application data and other display entities in a memory module as separate bit maps. A single image for display on a TV display screen is generated by overlaying all the display entities (including television signal, network application data, pointer, and low resolution data) according to a predetermined priority. Display entities (other than TV signal) are stored in separate portions of the memory module as independent surfaces to enable the displays of individual display entities to be generated and modified according to the individual display entity requirements.

Abstract: A phase comparator circuit which can compare the phase of a target clock signal with the phase of a reference clock signal with a short comparison cycle. An auxiliary waveform representative of the incremental phase of each of the reference and target clock signals may be generated, and samples on the auxiliary waveforms may be compared to determine the relative phase. The result of the comparison can be used to adjust of the phase of the target clock signal. As several samples can be taken on the auxiliary waveforms, the present invention enables frequent phase comparisons. The frequent comparisons may enable the target clock signal to be synchronized quickly with the reference clock signal. The invention has particular application in display units using phase lock loops (PLLs).

Abstract: An ATM switch supporting multicast transmissions and efficient transmission of frames. A cell is received on a multicast connection and transmitted on several branches/ports. Instead of copying a multicast cell several times for each output branch, only one copy of each multicast cell is maintained. The cell order and the stored cell data form a physical queue. Several logical queues are maintained, one for each output branch. In one embodiment, linked lists are used to maintain the queues. A cell in the physical queue is deleted after all logical queues traverse that cell. A shared tail pointer is used for all the logical queues to minimize additional processing and memory requirements due to the usage of logical queues. The queues enable cells forming a frame to be buffered until the end of frame cell is received, which provides for efficient handling of frames.

Abstract: A clock generation circuit for use in a television system displaying images encoded in television signals and images represented by network application data. The clock generation circuit generates a clock signal synchronized with HSYNC signals of the television signals. The clock generation circuit includes a phase-lock-loop (PLL) circuit and a tracking block. PLL circuit includes an oscillator (e.g., VCO) driven by an error signal to generate an internal periodic signal having frequency substantially equal to the frequency of the desired clock signal. The tracking block includes a resettable VCO (RVCO) driven by the error signal. A restart signal is asserted prior to the expected arrival time of the HSYNC edge to cause the RVCO to stop generating the desired clock signal. The restart signal is deasserted on receiving the HSYNC edge to cause the RVCO to start generating the clock signal. Accordingly, the clock signal is synchronized with the HSYNC signal.

Abstract: A clock generator circuit which provides for short comparison cycles even if X and Y do not have a large common denominator when a target clock signal having a frequency of (X/Y) times the frequency of a reference clock signal is to be generated. The comparison cycle is shortened by using approximately X/L and Y/L as divisors, instead of X and Y. As X/L and/or Y/L may not equal integers, multiple divisors may be used in a weighted fashion such that the weighted averages equal X/L or Y/L as the case may be.

Abstract: A digital display unit for minimizing the display artifacts which may be caused by aliasing of high frequency distortions present in wide bandwidth analog display signals. The minimization is achieved by modulating a sampling clock signal by different phase delay amounts for successive lines or frame. Due to such modulation, the analog display signal is sampled at different sampling points in different frames for the same pixel position. As digital display screens are typically designed to respond slowly to differing scanning intensities and as the human eye generally averages different color intensities at the same point, a low-pass filter effect may be in place with respect to the samples taken at the same pixel position. Display artifacts are minimized due to the sampling at different sampling points and the low-pass filter effect.

Abstract: A functional verification system suited for verifying the function of cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

Abstract: A method of recovering synchronization signals contained in a composite video signal. The synchronization signals are generally represented by voltage levels less than the blanking level of the video signal, and display data is represented by blanking level. A digital circuit controls a biasing circuit to generate a biasing voltage. A video signal is biased using the biasing voltage and the resulting biased video signal is provided as an input to an operational amplifier. A second input of the operational amplifier is driven by a reference voltage. The digital circuit monitors the output of the operational amplifier and controls the biasing voltage to cause the operational amplifier to clip the display data from the biased video signal and generate a signal representing synchronization signals.

Abstract: A memory controller for controlling accesses to a memory storing display entities including network application data displayed on a display screen of a television system. For performing a display screen refresh operation, the network application data is retrieved with a predetermined period. Accordingly, the memory controller determines an expected time for receiving the next request for retrieving the network application data for screen refresh. The memory controller blocks any lower priority memory access requests from a few clock cycles prior to the determined expected time. As a result, the requests for retrieving network application data can be serviced in an acceptable time.

Abstract: A television system for displaying images having adjacent horizontal blocks with sharp contrast. In general, such sharp contrasts can cause the drive voltage (Hv) applied to an anode of a CRT display unit to change. The changes typically result in distortions in the displayed images. A correction logic is employed to regulate the voltage source that supplies the voltage to the anode of the CRT display unit. The correction logic examines the digital data representation of the images to determine the extent of contrast, and supplies a corresponding correction voltage to regulate the voltage source. Due to the correction voltage, a constant drive voltage is supplied to the anode. The distortions are thus minimized or eliminated.