Patents Represented by Attorney Law Office of Charles W. Patterson, Jr.

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  • Duty cycle measurement circuit for measuring and maintaining balanced clock duty cycle
    Patent number: 7961559
    Abstract: A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert C. Dixon, Robert L. Franch, Phillip J. Restle