Abstract: An all-optical logic gates comprises a nonlinear element such as an optical resonator configured to receive optical input signals, at least one of which is amplitude-modulated to include data. The nonlinear element is configured in relation to the carrier frequency of the optical input signals to perform a logic operation based on the resonant frequency of the nonlinear element in relation to the carrier frequency. Based on the optical input signals, the nonlinear element generates an optical output signal having a binary logic level. A combining medium can be used to combine the optical input signals for discrimination by the nonlinear element to generate the optical output signal. Various embodiments include all-optical AND, NOT, NAND, NOR, OR, XOR, and XNOR gates and memory latch.

Abstract: A method of performing placement of resources in a computer-aided design (CAD) tool includes performing a first congestion analysis, proposing a placement move, and evaluating the placement move. The method further includes incrementally updating information used for performing another congestion analysis.

Abstract: An all-optical logic gates comprises a nonlinear element such as an optical resonator configured to receive optical input signals, at least one of which is amplitude-modulated to include data. The nonlinear element is configured in relation to the carrier frequency of the optical input signals to perform a logic operation based on the resonant frequency of the nonlinear element in relation to the carrier frequency. Based on the optical input signals, the nonlinear element generates an optical output signal having a binary logic level. A combining medium can be used to combine the optical input signals for discrimination by the nonlinear element to generate the optical output signal. Various embodiments include all-optical AND, NOT, NAND, NOR, OR, XOR, and XNOR gates and memory latch.

Abstract: A disclosed apparatus comprises a guiding element and a nonlinear element. The guiding element guides optical input signals, at least one of which is phase-modulated, to an interference area where such signals meet and interfere. The resulting interference signal is nonlinearly discriminated by the nonlinear element to produce an optical output signal that can be amplitude- or phase-modulated according to the phase modulation of the input signals. The invention also includes related methods and photonic logic gates.

Abstract: An all-digital serializer-de-serializer includes an all-digital clock multiplier unit (CMU) circuit, an all-digital clock and data recovery (CDR) circuit, a multiplexer (MUX), and a demultiplexer (DeMUX). The all-digital clock and data recovery (CDR) circuit couples to the all-digital clock multiplier unit (CMU) circuit. The multiplexer (MUX), couples to all-digital clock multiplier unit (CMU) circuit, and serializes data. The demultiplexer (DeMUX), couples to the all-digital clock and data recovery (CDR) circuit, and de-serializes data.

Abstract: A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD.

Abstract: Apparatus and methods for calculating power consumption of circuitry within integrated circuits (ICs), such as programmable logic devices (PLDs) are disclosed and described. A method of estimating power consumption of a circuit in an IC includes decomposing the IC into a plurality of overlapping blocks. Each block in the plurality of blocks includes a portion of the circuitry in the IC. The method further includes estimating power consumption of each block in the plurality of blocks, and estimating power consumption of the IC based on the power consumption of the plurality of blocks.

Abstract: A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

Abstract: An integrated circuit (IC) includes mechanisms for adjusting or setting the gate bias of one gate of one or more multi-gate transistors. The IC includes a gate bias generator. The gate bias generator is configured to set gate bias of one gate of the one or more multi-gate transistors within the IC. More specifically, the gate bias generator sets the gate bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract: A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.

Abstract: An integrated circuit (IC) includes one or more silicon-on-insulator (SOI) transistors. Each SOI transistor includes a first source region, a second source region, a drain region, a body contact region, a gate, and first and second isolation regions. The body contact region couples electrically to a body of the SOI transistor. The gate controls current flow between the first and second source regions and a drain region of the transistor. The first isolation region is disposed between the first source region and the body contact region. The second isolation region is disposed between the second source region and the body contact region.

Abstract: An integrated circuit (IC) includes a ring oscillator. One may tune the ring oscillator by controlling a power supply of the ring oscillator. One may further tune ring oscillator by varying a capacitance of at least one varactor. Using the tuning techniques, one may tune the output frequency of the ring oscillator to a desired frequency.

Abstract: Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.

Abstract: A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry and the programmable logic circuitry. The bridge circuitry further includes an information interchange circuitry. The first signal select circuitry is configured to selectably provide a communication path between the information interchange circuitry and either the programmable logic circuitry or the first interface circuitry.

Abstract: A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

Abstract: An integrated circuit (IC) includes a redundancy feature. The redundancy feature is provided by a redundancy circuitry within the IC. The redundancy circuitry is configured to provide the redundancy by using a decoder circuitry. The decoder circuitry receives and decodes coded defect information from a set of circuit elements adapted to provide the coded defect information.

Abstract: Apparatus and methods are disclosed for improving the performance of a programmable logic device (PLD). A PLD includes a memory cell configured to provide a pair of voltages to a gate of a pass transistor and a body of the pass transistor, respectively.

Abstract: An integrated circuit (IC) includes mechanisms for adjusting or setting the gate bias of one gate of one or more multi-gate transistors. The IC includes a gate bias generator. The gate bias generator is configured to set a gate bias of one gate of the one or more multi-gate transistors within the IC. More specifically, the gate bias generator sets the gate bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

Abstract: A programmable logic device (PLD) includes a non-volatile configuration memory. The non-volatile configuration memory is adapted to configure programmable resources (such as programmable logic and programmable interconnect) within the PLD. The non-volatile configuration memory may constitute a variety of memory types, for example, flash memory, erasable programmable read-only memory (EPROM), electrically erasable read-only memory (EEPROM), anti-fuse, and the like.